Circuit and Layout Co-Design for ESD Protection in BCD

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Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
9 W3 \* `# q7 S9 A2 V. C
Wen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE

' ~2 z- k3 F" c$ @& i( zAbstract—The n-channel lateral double-diffused metal–oxide–
! q- H2 g4 V5 U! v9 Ksemiconductor (nLDMOS) devices in high-voltage (HV) technologies
are known to have poor electrostatic discharge (ESD)
0 i# I1 \" x& m5 Rrobustness. To improve the ESD robustness of nLDMOS, a co-design
* o- [6 e; L; Gmethod combining a new waffle layout structure and a trigger
8 a1 ~* i" J, G' Z4 }5 tcircuit is proposed to fulfill the body current injection technique
/ \9 p$ o, t9 l  u$ r" M4 x, Bin this work. The proposed layout and circuit co-design method
9 O7 k* i1 k$ W) [. Ron HV nLDMOS has successfully been verified in a 0.5- m 16-V
! ~7 P3 M, Z- Dbipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
process without using additional process modification. Experimental
results through transmission line pulse measurement
+ P* |# Q/ r( `( G2 Rand failure analyses have shown that the proposed body current
. D: t# w# d6 R, Z$ E2 r' ]" xinjection technique can significantly improve the ESD robustness
2 q" @/ G) m5 j2 t% Qof HV nLDMOS.
! {( W/ r5 r4 k+ \1 k
; ~; Q% ^" M+ j% _! G9 t  oIndex Terms—Bipolar-CMOS-DMOS (BCD) process, body
1 j' @, U: n9 j' o% |current injection, electrostatic discharge (ESD), lateral double-diffused
- U" n. |% C! y6 n7 B  Emetal–oxide–semiconductor (LDMOS).

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