Circuit and Layout Co-Design for ESD Protection in BCD

semico_ljj

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process

3 Z$ P  q% r( O% ^8 hWen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE

Abstract—The n-channel lateral double-diffused metal–oxide–
semiconductor (nLDMOS) devices in high-voltage (HV) technologies
  O9 x5 q  @1 k9 Z/ u  Uare known to have poor electrostatic discharge (ESD)
# `8 B8 P; `1 F7 B7 a1 S( x: lrobustness. To improve the ESD robustness of nLDMOS, a co-design
method combining a new waffle layout structure and a trigger
circuit is proposed to fulfill the body current injection technique
! n/ X  ~- b1 din this work. The proposed layout and circuit co-design method
+ `* c, w  k) E. y4 }- von HV nLDMOS has successfully been verified in a 0.5- m 16-V
bipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
7 f2 H7 A' X: I' t& Sprocess without using additional process modification. Experimental
2 [0 U; ~0 o8 x/ W7 vresults through transmission line pulse measurement
and failure analyses have shown that the proposed body current
injection technique can significantly improve the ESD robustness
1 Y" ?. D8 ]) X' f/ Tof HV nLDMOS.

5 K  l1 {2 W6 d; G4 }! r+ IIndex Terms—Bipolar-CMOS-DMOS (BCD) process, body
current injection, electrostatic discharge (ESD), lateral double-diffused
metal–oxide–semiconductor (LDMOS).

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