Circuit and Layout Co-Design for ESD Protection in BCD

semico_ljj

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
( a& o+ @- t1 t$ u( x8 b
Wen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE

Abstract—The n-channel lateral double-diffused metal–oxide–
semiconductor (nLDMOS) devices in high-voltage (HV) technologies
, a7 n/ j7 M) C& I" ~are known to have poor electrostatic discharge (ESD)
; B2 o# C% f% Irobustness. To improve the ESD robustness of nLDMOS, a co-design
method combining a new waffle layout structure and a trigger
circuit is proposed to fulfill the body current injection technique
in this work. The proposed layout and circuit co-design method
on HV nLDMOS has successfully been verified in a 0.5- m 16-V
bipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
$ D8 E) {- i  L; Z$ L0 Aprocess without using additional process modification. Experimental
results through transmission line pulse measurement
" c8 f# v+ ?: W' ~+ q8 fand failure analyses have shown that the proposed body current
injection technique can significantly improve the ESD robustness
- h4 a6 S1 @( [0 o/ _. ]of HV nLDMOS.
, }( e- a+ C) @; S! n
Index Terms—Bipolar-CMOS-DMOS (BCD) process, body
current injection, electrostatic discharge (ESD), lateral double-diffused
) e+ x! G$ v9 b; y4 x' J  bmetal–oxide–semiconductor (LDMOS).

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