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Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
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Wen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE8 C! |2 k) k- G
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Abstract—The n-channel lateral double-diffused metal–oxide–9 Y% U ]- O9 q# [
semiconductor (nLDMOS) devices in high-voltage (HV) technologies
$ v5 k% Z6 O4 L$ [9 Mare known to have poor electrostatic discharge (ESD)
2 @) C( t5 ^, x! Lrobustness. To improve the ESD robustness of nLDMOS, a co-design
6 X4 o! f* L1 V3 e; ~/ x0 omethod combining a new waffle layout structure and a trigger$ {% L/ V1 `, E8 B, W( d8 v
circuit is proposed to fulfill the body current injection technique1 N$ [5 ~. V/ p$ \: H- H" ]; r
in this work. The proposed layout and circuit co-design method) s& y+ p/ z4 ^( M8 ~- A; M: Q
on HV nLDMOS has successfully been verified in a 0.5- m 16-V
( W0 t# u6 e0 s, @1 ^! p# jbipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD5 z: e& p: n; k: L6 c% e
process without using additional process modification. Experimental6 C4 e8 w! q' V; u8 T8 R+ V
results through transmission line pulse measurement: _, E8 X' X( `- n1 o
and failure analyses have shown that the proposed body current+ v- [( |8 p; c) ^% Z# z! H
injection technique can significantly improve the ESD robustness
3 j6 T5 T: b! G; h. ], ~of HV nLDMOS.
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Index Terms—Bipolar-CMOS-DMOS (BCD) process, body
$ i% Z7 u; I3 ?* lcurrent injection, electrostatic discharge (ESD), lateral double-diffused X7 D/ i. A) v- J0 l* Z0 r
metal–oxide–semiconductor (LDMOS). |
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