[關於] [jianping ]如何用verilog將變數前後補上幾個位元

tommywgt

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因為無法回覆, 所以開新文回答....
ABT={2'b00, DATA, 4'b0000};

" B; L) u+ t5 Z; V. l% Z5 x+ LVerilog 常用的operator
– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
– Logical operators: !, &&, ||
– 2’s complement operators: +, -, *, /, %
* E+ M9 n& g! \1 N! W– Relational operators: >, <, >=, <=, ==, !=, ===, !==
' y9 M  d! s" M4 a: }– Logical shift operators: >>, <<
– Conditional operators: ? :
; d9 m' X" a- Y8 y) s– Duplication operators: {n{ <exp> <,<exp>> *}}
' a1 z$ q: Y4 J) ^8 V0 }– Concatenation operators: {}
. z. x& I. |: S給你參考一下