[關於] [jianping ]如何用verilog將變數前後補上幾個位元

tommywgt

因為無法回覆, 所以開新文回答....
) A5 J6 A3 D( sABT={2'b00, DATA, 4'b0000};

Verilog 常用的operator
+ e! U6 D9 U9 O. L' m3 n. \– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
0 H" ]+ Q; k: G/ a– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
– Logical operators: !, &&, ||
! e! c: l6 d9 t, t5 S7 X. O– 2’s complement operators: +, -, *, /, %
– Relational operators: >, <, >=, <=, ==, !=, ===, !==
' u' x, X2 \6 a+ a7 h; j, s' I– Logical shift operators: >>, <<
) s- a' `7 h0 e' i- B– Conditional operators: ? :
( H, i% ^1 _8 e7 X; K" t– Duplication operators: {n{ <exp> <,<exp>> *}}
3 P7 w8 R$ n% g– Concatenation operators: {}
3 @7 O1 N, u7 x. G  r給你參考一下