[關於] [jianping ]如何用verilog將變數前後補上幾個位元

tommywgt

因為無法回覆, 所以開新文回答....
ABT={2'b00, DATA, 4'b0000};
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# f5 J" A. t6 r0 lVerilog 常用的operator
– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
7 `5 v/ }# S3 M% A: i: V+ ]" P– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
- {, o" w8 f% w: p( Q! m" p3 D4 z– Logical operators: !, &&, ||
% @: U! X" W, J– 2’s complement operators: +, -, *, /, %
– Relational operators: >, <, >=, <=, ==, !=, ===, !==
- H8 k: G8 h/ \2 v) j2 q– Logical shift operators: >>, <<
) l* _: z5 e8 f– Conditional operators: ? :
# {* i* w; E# f+ U– Duplication operators: {n{ <exp> <,<exp>> *}}
3 K( [1 i3 h* A6 b6 r2 F– Concatenation operators: {}
給你參考一下