[關於] [jianping ]如何用verilog將變數前後補上幾個位元

tommywgt

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因為無法回覆, 所以開新文回答....
ABT={2'b00, DATA, 4'b0000};

Verilog 常用的operator
– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
6 H# Z0 M8 a7 y- t6 T9 r: L– Logical operators: !, &&, ||
– 2’s complement operators: +, -, *, /, %
– Relational operators: >, <, >=, <=, ==, !=, ===, !==
" ?; z  y, T; S' W. A– Logical shift operators: >>, <<
– Conditional operators: ? :
– Duplication operators: {n{ <exp> <,<exp>> *}}
– Concatenation operators: {}
給你參考一下