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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題; ~* e. X5 g% |
" H. \1 n0 _; c$ j9 W
請教業界各位先進
  n+ ?! c8 Z( Q# I: g. @+ y$ {目前的chip開發,需要多少投資?) K# X5 T( ~1 w5 `" x
首先是假設 Febless design house.! v3 g; O9 K$ h# D3 Y
自家由algorithm 到 RTL simulation 完成
4 O; N' r1 B7 C9 \後端包給 backend service 公司 (layout, mask, Fab, assembly..)
/ D+ S2 o6 j" ~0 m以 ARM9 or ARM11, AMBA2.0 為platform
# G) N1 `$ h* t( K那麼- m, h% l+ X. f& Y+ H2 ^4 v
  (1)90奈米, NRE大概多少?
- n0 G6 z4 F3 |! ~+ c" r  (2)65奈米, NRE大概多少?
. i9 b: I/ p/ n- p: N) y; \  (3)或是您知道其他製程, NRE大約多少...; K# z6 e  i: p: ~( a

# f3 _* Z5 O% H9 R( y2 F謝謝
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?! `% n& O7 C* f0 S: [
How many mask layers it will be?/ e( J( L  l2 O+ Z
Besides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?2 P+ E( n5 ~2 i" {: B
How many chips you need? A full set mask or MPW?1 c3 d  J  ]9 @/ Z. E
What package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,
8 i' o+ \* c2 r1 u4 E- @9 ]
  M2 M( `. {$ J6 z1 c" {" E+ tI just estimate the investiment of a ASIC team.
+ ?- _' j# N( ]9 Nnot servey for a project.
6 z& Z3 @- w8 Z6 J: G- i  U' GSo, I just want to know the range of NRE.
4 L; D& r5 h6 M7 \* ~. Q1 h
2 j6 I7 X) r% |9 Z" r9 ~! cFor example, It will be : z, a0 V4 A8 g# C
(1) 5,000,000 NT$ ?5 B4 M2 _' n) B; N  @: ]
(2) 8,000,000 NT$ ?
# q. ?: I& N# f( C+ k(3)10,000,000 NT$ ?( ?4 a2 C% e% O& ?1 b: Z
(4)12,000,000 NT$ ?2 _" p  ?6 V/ h) y/ y/ x1 k
(5)15,000,000 NT$ ?" m  [# Q& o. N4 T

( Y% `' K$ X$ X$ I- h2 ESure, I understand following things:, X* C$ G) l2 o8 z" T  x& j$ G
- full set mask cost more
7 [) }: a0 R# k( E - PLL/LVDS... analog IP are extra cost
- v- A! E% Y( ~& d$ L - pin-count and area also influence cost
. \# k  h4 X! O, t" e - different package also cost different
9 c- {6 r4 O' n/ {- e; M, M+ W7 _* i5 d  D3 N
Therefore, if really need information for estimate,
7 f$ d3 N% Q$ A- D4 d! `3 P0 Rjust for example.7 k0 R8 p6 ~( N
Let's assume a SoC for FullHD TV application
8 N) p' i' W/ Rit will include
6 B" {) W7 C5 {6 U6 y3 J  - ARM AMBA
% L: [0 o- b8 L$ Q9 G! ^6 B/ y% A  - DDR2 I/F
3 x+ D( h5 ~! `& v  - GPIO, IIC,...5 Y3 z( k6 s6 c8 t1 J
  - LVDS out (dual link)
( R, O7 D9 g( e9 h  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,% u2 t; D. T& Z* b0 e: O! w  F
  - 12bit ADC, 10bot ADC x28 J# i0 \$ E% E1 b8 l
  - PLL/DLL
/ @0 n, a5 \3 S. i$ O$ F" D. w  - 256 pins 以上  @. o( }2 l% R5 _" `( L, h
  w# q! `$ [1 w8 t( H) v( N
Than,... any idea about NRE fee?! e# m$ ]5 U# j5 V( o$ `* U+ ]
again, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,2 K, j7 d6 V. T* z1 R/ |% Q4 a
basically 65nm-->USD$1M above and 90nm-->700K above
) r  M; o" v2 L! e+ |( q3 Mand base on different foundry has difference price!- Z  D3 K6 @9 P
this price did not include any specific IP like TV encoder, decoder, vedio codec....
( s9 f( F1 R1 y+ G! e' I. K9 Mand did not include the ARM licensee...- ^; C, M) A* p1 P; |2 j0 R3 B
actually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)
* ?3 [$ k6 i3 \1 `6 O8 p+ I  b( Hand package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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