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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題4 G* M& n# C+ e* }! o  Q, j

9 }/ \4 Q* B4 E* g0 S6 \請教業界各位先進
% ~: M3 C7 s8 R目前的chip開發,需要多少投資?
/ w! J! t' [) V首先是假設 Febless design house.& L& p) B5 A. l- z' ]' _
自家由algorithm 到 RTL simulation 完成5 ?+ w# y- Y  ~/ q
後端包給 backend service 公司 (layout, mask, Fab, assembly..)2 z& e! t1 i; r  n, ?
以 ARM9 or ARM11, AMBA2.0 為platform2 E1 m" o  r3 G8 [- g- {
那麼
& [) d* Q; ~* k/ K) x  (1)90奈米, NRE大概多少?
3 I" A: z9 }( L4 A  (2)65奈米, NRE大概多少?+ k) I4 O; B6 w  l& `7 N& @4 w
  (3)或是您知道其他製程, NRE大約多少...8 f' o0 I" b$ u* Y; U' G' O
/ r9 t5 S+ N: g, q) h; r( }
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?
5 c3 ?, t* O6 o  u% b9 B, b+ J: pHow many mask layers it will be?) o, x- D5 d& f% j1 h8 Z
Besides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?3 B2 h0 w# I1 k
How many chips you need? A full set mask or MPW?: H! ]/ J7 [* ~$ ~' [
What package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,
; L% |4 H3 O/ o6 L! r. i
. V$ A, }  G6 e& c8 `5 fI just estimate the investiment of a ASIC team.
9 h: @7 L4 z; T, l' Pnot servey for a project.
7 E6 S4 }/ }( h: K( s6 xSo, I just want to know the range of NRE.
  Z- d! z# {. d9 U2 I- C+ U1 A" H0 U  Z% H
For example, It will be
  h- T+ N' J- ]" [9 L$ p(1) 5,000,000 NT$ ?- u9 `6 \' t! W: f: v
(2) 8,000,000 NT$ ?
3 R8 g9 |) T4 L0 {; k' B% q(3)10,000,000 NT$ ?2 n0 f% f+ v8 m' d
(4)12,000,000 NT$ ?6 c* A* T$ x5 t( Y3 ^5 L
(5)15,000,000 NT$ ?- v, K8 b. ?2 u0 H; G2 M

6 l& w# `% V7 H1 _Sure, I understand following things:
5 z' A, E+ |, [9 H* _ - full set mask cost more4 K7 F) c( i0 ]6 \5 m, F
- PLL/LVDS... analog IP are extra cost% d: [) z4 q+ l
- pin-count and area also influence cost
% t2 I, w' V5 w9 m+ R - different package also cost different9 W* c- w; V  k% u3 B" H
, {: t6 n; B( U9 h( |  [" m
Therefore, if really need information for estimate,( L& n$ E! D8 m9 o. v' g
just for example.
7 q5 \- P* c  v9 {4 |9 O+ dLet's assume a SoC for FullHD TV application
2 ?3 K# G7 [, b7 c5 K1 \$ |it will include4 E# o: m' I1 f8 p8 v0 X
  - ARM AMBA5 e* p6 R- G6 h* x0 A, t3 i5 z
  - DDR2 I/F
! @( S& H; k3 ^9 S% b  q2 ?9 ?  - GPIO, IIC,.../ i7 w5 b) ?7 W3 W
  - LVDS out (dual link)
2 b0 {: L& M/ [& d& Y. A& k* y! e  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,
" w" G& @3 m! E7 z% I! m  - 12bit ADC, 10bot ADC x2: g$ l  B% I# [! B! E
  - PLL/DLL! h* s; J0 a8 k, z
  - 256 pins 以上/ o+ J4 ?" o: N5 `8 l
- {$ H0 M: z* {) t3 q+ p
Than,... any idea about NRE fee?1 b3 J* Y( r% J% K. a
again, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,
4 w- z* ^0 h# G* I0 Q3 A+ Cbasically 65nm-->USD$1M above and 90nm-->700K above
% j, C# `* M1 i# m0 f0 c1 z3 Cand base on different foundry has difference price!
) x( J; c* v, I& Z# x( B4 ?this price did not include any specific IP like TV encoder, decoder, vedio codec....# F+ c( p+ v2 u2 v
and did not include the ARM licensee...
3 t5 i" }7 ?8 z1 ^( r2 |- Mactually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)- y/ \2 w. Q& [1 z1 t4 s) P
and package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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