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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題
3 s  Q7 E7 H+ m( O+ t# [4 C1 u( d7 a5 M3 {7 e" ?
請教業界各位先進
" i/ B6 ?5 \% Z/ m  p5 B9 Z  M目前的chip開發,需要多少投資?8 D5 P& e- }: _: ?( t# k
首先是假設 Febless design house.2 @4 s5 ^' d6 ^- s
自家由algorithm 到 RTL simulation 完成
4 T" X7 }0 Z# Y, F後端包給 backend service 公司 (layout, mask, Fab, assembly..)
0 x* S: g2 d) g, e( T- L  a以 ARM9 or ARM11, AMBA2.0 為platform- d( f$ [9 {' }+ E. R
那麼
8 H( n2 b) V8 e8 G" x9 P& j  (1)90奈米, NRE大概多少?6 B: N. g- I: W( \/ s4 s3 y  `; q5 Y! m
  (2)65奈米, NRE大概多少?+ f8 D3 J3 ?& p0 {# s8 ]4 _; a
  (3)或是您知道其他製程, NRE大約多少...
2 L5 A3 @8 R/ U9 \7 t/ W' W- t, }& D6 \
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?
- R1 b3 N7 ~7 K1 E# r  @8 A6 wHow many mask layers it will be?* U0 H8 k- [& q6 o0 P& C& w
Besides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?- o+ A" o* ?/ X4 Z4 a7 y7 ^" O
How many chips you need? A full set mask or MPW?9 ?. `$ L0 N+ g( G
What package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,
3 `6 V3 d& n( l: R8 r1 _* A7 v: d2 K+ a' V- N
I just estimate the investiment of a ASIC team.
" `" O1 h3 [, v' K) ]1 g2 ?not servey for a project.
3 H. J5 |5 Q: \# [% W( MSo, I just want to know the range of NRE.
6 n" e7 {+ Q5 D$ p8 W$ Q
: l4 X. W& Z% p; a' ^: p# JFor example, It will be
+ l3 H* E0 ]1 U7 {2 m! R, ]* ~(1) 5,000,000 NT$ ?
5 A( l) m' \% e+ o; V8 ~9 {" r; z(2) 8,000,000 NT$ ?
" s( N+ P9 g- M(3)10,000,000 NT$ ?. I9 X. Z- D- r
(4)12,000,000 NT$ ?
5 _5 w7 p6 G, a# ^! }' U; E; N3 ^(5)15,000,000 NT$ ?
7 T0 y  {7 n7 h2 T9 J: P( j
. M, O& e' M: d1 `; {# ASure, I understand following things:
" U# Y) H9 [: l1 m - full set mask cost more
8 l  H& ^  {" N  x9 n7 M. | - PLL/LVDS... analog IP are extra cost. Y: W/ f( D2 V
- pin-count and area also influence cost" }( I# K0 ^$ |- l% j% ?
- different package also cost different2 w; M" `, [" [5 |
* M. F5 G  d1 G' J
Therefore, if really need information for estimate,
3 A1 o. J, y9 A8 ~) I$ |9 Fjust for example.
7 h1 J% T( A, ^7 }# V1 ILet's assume a SoC for FullHD TV application% T/ M+ K; J# T4 i
it will include' x9 P5 f6 H) F" h* s+ B2 d( y$ N
  - ARM AMBA2 ]! y2 e0 Z# Z: z( y& P9 Q( _' N  a
  - DDR2 I/F! m6 h( `# ~0 j3 _
  - GPIO, IIC,...
: [$ z8 ~! F4 R$ j% h, Z5 q  - LVDS out (dual link)
. W2 z7 D; W3 U- i2 U- J  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,
$ s6 y  n% u9 V4 {  l7 N  - 12bit ADC, 10bot ADC x2! ^. |( C# @( {! ~1 P* ?9 K: E
  - PLL/DLL! {' E0 d9 o2 l" u" h
  - 256 pins 以上
& W7 R8 E' i9 ^+ W) t2 L/ f1 @& }! w
Than,... any idea about NRE fee?$ x" A. w$ E7 r9 u% \0 w/ u
again, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,& Z( \& E4 c  L* T7 ?1 p5 a
basically 65nm-->USD$1M above and 90nm-->700K above
9 [+ E; l( u5 r& Land base on different foundry has difference price!; N8 F2 B# z7 Y; _2 L2 @, O
this price did not include any specific IP like TV encoder, decoder, vedio codec....
, ~& t- K% c3 p3 u) E; Iand did not include the ARM licensee...
6 ^- C/ ^- o6 L* I2 @% c+ ~) k# v) c: ^4 Gactually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)' I5 B) a) C! ^, ^* P- c5 L; V
and package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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