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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題4 |% B. ^$ Y! f0 h) X5 h+ [
4 a3 d- N2 I& H. \% d- g0 v+ Q
請教業界各位先進/ s* n. }0 [6 }, p
目前的chip開發,需要多少投資?; t( M9 G4 |+ N9 t
首先是假設 Febless design house.
2 K# A. M% E- M自家由algorithm 到 RTL simulation 完成
& p" S% s+ G$ ~9 _. h+ n# X( q後端包給 backend service 公司 (layout, mask, Fab, assembly..)
6 R3 g8 B9 y6 K! H以 ARM9 or ARM11, AMBA2.0 為platform
( l- e$ A: P/ j- O那麼
( ]$ f5 a8 B! _5 `2 B  (1)90奈米, NRE大概多少?5 p. d2 |8 q$ M/ a$ u$ S7 M
  (2)65奈米, NRE大概多少?0 S. W$ w3 Q9 A
  (3)或是您知道其他製程, NRE大約多少.../ _+ g& m( [$ a2 E' k

# L( ~4 z/ G+ [6 }4 r謝謝
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?
" k8 x; V% i( ]How many mask layers it will be?
- q3 j; o3 z3 F, jBesides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?
$ C7 R, O% i9 ^- B: O7 W% THow many chips you need? A full set mask or MPW?. R. }  n6 K% b; g- n9 {
What package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,
( F1 a$ H  E2 z% A0 \) O0 t. J, N! J* W
I just estimate the investiment of a ASIC team.
: k' h) t# u: o; ~not servey for a project.
& A! S* ?% @* G/ R, JSo, I just want to know the range of NRE.* C1 _5 Q+ _& L# S( c6 l; x7 O

4 }' |+ ^0 q, e  P& }2 Q9 ZFor example, It will be 4 r& r% ?7 g) j( n' e( ~
(1) 5,000,000 NT$ ?
" c& C4 Y( F2 {: z, Z  [  n(2) 8,000,000 NT$ ?" L7 M9 J0 J0 _- H0 p
(3)10,000,000 NT$ ?7 O- L5 ~' \) x/ [! v, ?! q
(4)12,000,000 NT$ ?
3 o6 S8 q" m% U7 I(5)15,000,000 NT$ ?
% u' ^6 S* X) C! {
: v6 k% ~5 G. p$ U9 Y. B# zSure, I understand following things:6 y/ K& v: N' j3 Q, Y) e& R
- full set mask cost more( b0 T0 K4 Y' X6 O2 Z7 y
- PLL/LVDS... analog IP are extra cost
: ^2 N' y" ]5 p( B( f2 K  i - pin-count and area also influence cost6 i: N; U; S" k; I4 l# a8 ~+ p" P
- different package also cost different% ^& Z0 n' B5 X% X

9 p1 A1 n4 f6 u$ h; R) PTherefore, if really need information for estimate,
6 W" V4 i# d1 U6 a. `  _" E/ }just for example.( C3 l$ I8 ]4 i! Q7 I7 ?- _7 X8 d2 X/ d7 ^
Let's assume a SoC for FullHD TV application
$ m- N5 ?  d" I2 a' p! kit will include! X  e$ D7 E, s
  - ARM AMBA/ `" x7 K% Y( v. r* a5 ^
  - DDR2 I/F( k* ~+ Z% ]6 c7 K- z, O3 P% q) t
  - GPIO, IIC,...
- q+ `. d# q2 [2 ~' l2 y  - LVDS out (dual link)& c2 m# l$ R0 {
  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,5 [, ~- o7 P8 f: J7 ~, D
  - 12bit ADC, 10bot ADC x2
/ ~6 z( u3 s* a1 e  - PLL/DLL1 N5 [: W5 R. e4 t- m9 W/ g( w
  - 256 pins 以上% `& n( I- p* C) p

. p* H' D5 o  K8 Y" Z! PThan,... any idea about NRE fee?7 s6 X# F- E0 q* q: `9 [
again, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,
( H, X/ r0 o* n6 ]basically 65nm-->USD$1M above and 90nm-->700K above
- x# ?1 c3 [) X  ?4 w, w  c) qand base on different foundry has difference price!
2 q$ a* Y% h7 h5 q+ c) n* rthis price did not include any specific IP like TV encoder, decoder, vedio codec....# c: y; d: B. N
and did not include the ARM licensee...
# Q9 O9 [4 D3 N! h4 Jactually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)
' F- y4 N" \( B- W, H2 I, iand package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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