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In order to save test device, usually will do Power to Ground then IO to Power/Ground and the last is Io to IO.
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( g- ~* K, n$ n( mThe reason is:
# x* n% y7 M- a4 z& ?4 P1. If power to ground can not pass, the rest combination has less chance to pass+ X4 ^: W* @$ u2 [( V3 T5 N4 @
2. Usually power pin count is less than IO pin count. It is fast to get an idea how the chip's ESD level& m3 j( \- {, v- p5 D, _
3. If failed, it's easy to find the failed ESD zapping combination |
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