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In order to save test device, usually will do Power to Ground then IO to Power/Ground and the last is Io to IO. 5 c, ]( z7 d5 `& o
" W2 u8 y+ U7 ^# {
The reason is:
# M. B; x+ t1 x4 M* m1 \1. If power to ground can not pass, the rest combination has less chance to pass
: |8 U) u$ @, [, L5 d- M2. Usually power pin count is less than IO pin count. It is fast to get an idea how the chip's ESD level" H# B2 ~1 Y. U0 y
3. If failed, it's easy to find the failed ESD zapping combination |
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