Verilog 宣告的小問題~

kokonut · 發表於 2009-6-2 18:13:59

就是我在跑Modelsim的時候

會出現以下訊息

# -- Compiling module LD_feedback_0601
# ** Error: ld_feedback_0601.v(29): 'bias_set_t' already declared in this
scope (LD_feedback_0601).
# ** Error: ld_feedback_0601.v(1): Identifier must be declared with a port
mode: bias_set_t.
# ** Error: C:/ispTOOLS7_0/modelsim/win32loem/vlog failed.

他指的是我bias_set_t宣告上有問題

可是我以前這樣宣告都正常阿  ~"~

感謝解惑~

...........orz

=============<程式碼~~~黃色部分~~~!!!>==================
module LD_feedback_0601(clk,rst,E1,E2,p,q,p1,q1,bias_set_t,show_a_t);

input clk,rst;

input[7:0] E1 ;
input[7:0] E2 ;
input[7:0] p ;
input[7:0] q ;
input[7:0] p1 ;
input[7:0] q1 ;

wire[15:0] k1;
wire[15:0] k2;
wire[15:0] k3;
wire[15:0] k4;

assign k1 = E1 *(q - q1);
assign k2 = E2 *(p - p1);
assign k3 = E2 * p1;
assign k4 = E1 * q1;

//////////////////////////////////
reg[7:0] bias_set = 8'd8;
wire[7:0] bias_set_t;
output[7:0] bias_set_t;

assign bias_set_t = bias_set;

reg[3:0] show_a;
output[3:0] show_a_t;
wire[3:0] show_a_t;

assign show_a_t = show_a;
//////////////////////////////////

always@(k1 or k2 or k3 or k4)

begin
   if(!rst)
   begin
   show_a = 0;
   bias_set = bias_set;
   end
   else if(k1 == k2)
      begin
            if(k3 == k4)
               show_a = 3;
            else if(k3 > k4 || k3 < k4)
               begin
               show_a = 0;
               bias_set = bias_set - 1;
               end
      end

kokonut · 發表於 2009-6-2 22:56:34

感謝樓上...orz

真的OK了~

我還需要多多加強~!!!

Pegasus222 · 發表於 2009-6-2 18:50:13

請改順序如下試試

output[7:0] bias_set_t;

wire[7:0] bias_set_t;
assign bias_set_t = bias_set;

Good Luck !

[ 本帖最後由 Pegasus222 於 2009-6-2 07:29 PM 編輯 ]

kokonut · 發表於 2009-6-2 18:16:03

宣告部分用黃色太失敗了

我重貼原文黃色部分

//////////////////////////////////
reg[7:0] bias_set = 8'd8;
wire[7:0] bias_set_t;
output[7:0] bias_set_t;

assign bias_set_t = bias_set;

reg[3:0] show_a;
output[3:0] show_a_t;
wire[3:0] show_a_t;

assign show_a_t = show_a;
//////////////////////////////////

kokonut · 發表於 2009-6-2 18:15:04

else if( k4 > k3 )
            begin
                     if( k4 - k3 > k2 - k1 )
                        begin
                              show_a = 2;
                              bias_set = bias_set + 1;
                        end

                     if( k4 - k3 < k2 - k1 )
                        begin
                              show_a = 0;
                              bias_set = bias_set - 1;
                        end

                     else if( k4 - k3 == k2 - k1 )
                        begin
                              show_a = 1;
                              bias_set = bias_set ;
                        end
            end
      end

end

endmodule

kokonut · 發表於 2009-6-2 18:14:50

else if(k1 > k2)
      begin
         if( k3 < k4 )
            begin
               show_a = 0;
               bias_set = bias_set - 1;
            end

         else if( k3 > k4 )
            begin
                     if( k3 - k4 > k1 - k2 )
                        begin
                              show_a = 0;
                              bias_set = bias_set - 1;
                        end

                     else if( k3 - k4 < k1 - k2 )
                        begin
                              show_a = 2;
                              bias_set = bias_set + 1;
                        end
                     else if( k3 - k4 == k1 - k2 )
                        begin
                              show_a = 1;
                              bias_set = bias_set ;
                        end
            end
      end

   else if(k2 > k1)
      begin
         if( k4 < k3 )
            begin
               show_a = 0;
               bias_set = bias_set - 1;
            end

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[問題求助] Verilog 宣告的小問題~