Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes

Karan Bhatia and Elyse Rosenbaum
Department of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
: Y3 _2 a1 @4 A$ B# ~1 `2 I* d1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu
8 v  g; ]9 I$ r2 n, Z- U" K, h
9 @4 k# e- Y& s7 `2 R1 O7 lAbstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
investigated. The current compression point (ICP) is introduced to define the maximum current handling
$ E+ s6 y7 x9 H0 ~! s6 ?5 ]; H2 Qcapability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
: `! _8 i$ D" r1 |) b& \6 Y: Aperformance of the structures investigated herein.

semico_ljj

The dual-diode circuit has been found to be a suitable
ESD protection circuit for GHz-frequency CMOS
% v% T6 ]5 `0 Y+ L% vI/Os [1]. Layout-optimized ESD diodes provide a
4 V: S7 j) p& }" [5 }: `high protection level per unit capacitance (C),
minimizing the performance degradation they induce
on high frequency I/O pins.