Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes

Karan Bhatia and Elyse Rosenbaum
2 t" n3 C$ P6 N6 F/ eDepartment of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu
( a2 [' X7 Q3 `  k7 F2 F5 J
) J. q. l2 }6 n% r% D1 R  k) yAbstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
5 j) M/ b8 z2 C2 m) kinvestigated. The current compression point (ICP) is introduced to define the maximum current handling
capability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
8 Z# P; y6 d7 r1 |9 tperformance of the structures investigated herein.

semico_ljj

The dual-diode circuit has been found to be a suitable
ESD protection circuit for GHz-frequency CMOS
! e0 \8 M% ]) d, Q# q) j8 }- zI/Os [1]. Layout-optimized ESD diodes provide a
. H% q( |: T6 y! r+ D, Ghigh protection level per unit capacitance (C),
minimizing the performance degradation they induce
on high frequency I/O pins.

mousestack2003

感謝大大分享這些資料∼
7 |& [6 v% g+ j7 Q5 p7 `
讓我們了解led的一些事情∼

majorchen

權限不夠,真想看看layout guide要注意什麼...
6 R; S1 T2 R: G0 U* t$ `真是可惜...

guillermo

感謝樓主的分享!小弟最近剛好遇到ESD的問題!

dike

真想看看  與工做相關
小弟最近剛好正在研究ESD中  謝謝

allenearl

发现一个很好的网站,有很多EMC&ESD设计方面的资料,完全免费的.
www.gooemc.cn

hing

很棒的參考資料，謝謝分享！

yoyoseven

謝謝你的分享
. V* e  ^3 ~; H- t) p! K現在急需esd的防護方式