Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes

Karan Bhatia and Elyse Rosenbaum
3 R7 S0 t5 M- R% x: K& W" l" dDepartment of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu
/ t7 c7 [* L' M! A$ U0 ^9 s
- k9 Q5 U' Z# ]( _  ~& qAbstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
investigated. The current compression point (ICP) is introduced to define the maximum current handling
capability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
performance of the structures investigated herein.

yoyoseven

謝謝你的分享
6 _  @% f% _1 Y8 S4 A  v& q% Q現在急需esd的防護方式

hing

很棒的參考資料，謝謝分享！

allenearl

发现一个很好的网站,有很多EMC&ESD设计方面的资料,完全免费的.
www.gooemc.cn

dike

真想看看  與工做相關
小弟最近剛好正在研究ESD中  謝謝

guillermo

感謝樓主的分享!小弟最近剛好遇到ESD的問題!

majorchen

權限不夠,真想看看layout guide要注意什麼...
, m' v9 }) z. x3 j2 i* _# x! M真是可惜...

mousestack2003

感謝大大分享這些資料∼

讓我們了解led的一些事情∼

semico_ljj

The dual-diode circuit has been found to be a suitable
ESD protection circuit for GHz-frequency CMOS
4 L# C6 ]- a& Y% f# ~, {I/Os [1]. Layout-optimized ESD diodes provide a
high protection level per unit capacitance (C),
* w& n( m! u3 B7 Ominimizing the performance degradation they induce
on high frequency I/O pins.