Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes
( Q6 i9 k! F3 j& g  m
7 N8 ?+ R2 W) X/ m! _Karan Bhatia and Elyse Rosenbaum
Department of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu
" G) q# v9 I( x3 J
Abstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
investigated. The current compression point (ICP) is introduced to define the maximum current handling
2 n# c; Z$ e  ocapability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
performance of the structures investigated herein.

yoyoseven

謝謝你的分享
2 Q* b. o$ V8 }# B4 A2 H2 S& k2 e現在急需esd的防護方式

hing

很棒的參考資料，謝謝分享！

allenearl

发现一个很好的网站,有很多EMC&ESD设计方面的资料,完全免费的.
www.gooemc.cn

dike

真想看看  與工做相關
小弟最近剛好正在研究ESD中  謝謝

guillermo

感謝樓主的分享!小弟最近剛好遇到ESD的問題!

majorchen

權限不夠,真想看看layout guide要注意什麼...
真是可惜...

mousestack2003

感謝大大分享這些資料∼
3 b, K/ q% h3 B: m! e( }/ r2 \
6 d2 [" o2 t# @4 E! E6 W讓我們了解led的一些事情∼

semico_ljj

The dual-diode circuit has been found to be a suitable
ESD protection circuit for GHz-frequency CMOS
7 D5 Y$ u. Z- |. x& X- uI/Os [1]. Layout-optimized ESD diodes provide a
high protection level per unit capacitance (C),
2 V. y& b) J$ i7 Fminimizing the performance degradation they induce
on high frequency I/O pins.