Berkeley的一篇博士论文_Jitter Reduction on High-Speed Clock Signals

hitxiaojun

This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter
Attenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
% s# \7 K1 V) O* D5 p; [on par with commercially available PLLs, while being relatively simple to design and use as
+ P- {3 p. p( c! _# t1 Fan on-chip solution. The main difference between the JAC and PLLs is that the JAC does
not guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In
4 ~0 |+ B7 U7 I  nthe following sections the effects of jitter, present methods to reduce jitter, and application
of the JAC will be discussed.
$ G3 a6 V1 t: S# s! J" \

遊客，如果您要查看本帖隱藏內容請回復

microuser

感謝大大無私分享，剛好需要看PLL jitter 學習一下 感謝！

microuser

感謝大大無私分享，剛好需要看PLL jitter 學習一下 感謝！

microuser

感謝大大無私分享，剛好需要看PLL jitter 學習一下 感謝

alienwarejian

谢谢
6 y/ p3 z! m! D; f2 c* z谢谢

ja1688888

剛好需要看PLL jitter 學習一下 感謝

starfish311

回復 1# hitxiaojun

- M/ j. r1 K. Y8 k5 w8 `$ ~& o0 k* [
    謝謝你的分享，希望會有所幫助

lyx1982

谢谢分享！收藏了！！！

xp212125o

thank you~
感謝分享
正好有需要

anita66

感謝大大無私分享, 不知道有沒有跟Thomas Lee的論點是否相同??3Q~

eceking

可惜沒足夠的錢幣............................................................!

ychchip

jitter is important issues in analog ic design.  it must be carefully designed including path match and high speed.

donnie

Thanks for Sharing!
Thanks for Sharing!

donnie

Thanks for Sharing
Thanks for Sharing

b56389

多看看別人所推薦的paper
. s; B+ V: r! w! c4 C研究其的看法與理論
- W; N: ^7 O& g相信對增進自己的實力有幫助的

godman

謝謝你的分享，希望會有所幫助。

planet1114

最近在工作上一直被noise所困擾,
! p# [, Z* w, `下來看看能不能從這有新的啟發.
% A! M) U$ u( |) R( u# i先謝啦

anita66

Wow, 新的耶?!真是太讚了, 先下來study看看, 有機會在跟大家分享心得, 3Q~

liyao

> < 我很少上來 沒錢下載 怎麼辦呀!!

liyao

剛好工作上碰到jitter measurement問題,下載參閱一下,感恩!!