|
This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter0 T0 Y& H) \" A4 ^
Attenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
5 V0 m- ^( n. q' j0 jon par with commercially available PLLs, while being relatively simple to design and use as
% j* e% C' m$ Z3 u4 E4 J, e- O! z9 man on-chip solution. The main difference between the JAC and PLLs is that the JAC does
& \& c7 `! |; O8 r3 Fnot guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In: D I& E: p5 ~8 h) P( q
the following sections the effects of jitter, present methods to reduce jitter, and application) @! T$ Z! M1 r+ n
of the JAC will be discussed.7 E3 _4 v; c5 F4 t" P, R& K8 B; d
# s* F! a8 A+ K) ?# m: |- e9 _
|
本帖子中包含更多資源
您需要 登錄 才可以下載或查看,沒有帳號?申請會員
x
|