VHDL 初學者問題

matmat

想COMPILE一個簡單的latch circuit

1 Q2 u# g4 Q4 i, m先execute了每一個file
(如附件中, 3個file
1 f2 R6 W5 C3 r( n8 ^( N$ Clatch.vhd
tb_latch.vhd
cfg_latch.vhd)
! @1 Y. z* A; T  P/ e都沒有問題,
可惜到compile那part就出現問題(如下)
4 o4 e- G/ P6 ^/ u+ y7 l有沒有高手可以幫我解釋?   
" T% X0 e5 P  Y% ^; Q) E
Cannot find specified design unit (TB_LATCH) to elaborate.
        Please ensure you have specified the correct design
; }4 _! {' \2 R8 X9 U1 a9 G/ \        unit name and that it has been analyzed into the correct
        VHDL library.