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Startpoint: U_RST/nResetUSB_reg
% x, w& i" D; R7 e( Q3 C (falling edge-triggered flip-flop clocked by CLK48)
# q9 H$ G& d& \/ N Endpoint: u_FUSB/FUS/BIF/PS/q_reg_2_
' F+ [0 K7 o, ~ (rising edge-triggered flip-flop clocked by CLK48)8 |; v6 x$ z3 M! {6 d1 o
Path Group: CLK48
8 A& u+ C5 ]- x9 d( h; a& L Path Type: max X2 N' w, X7 ?8 S) }4 b" k D- m
& z/ x6 \+ ?& ~+ Y! s1 V8 g8 \
Point Incr Path9 z% M3 p: _9 l" w
--------------------------------------------------------------------------( V( f2 f& f2 r1 z L! f8 {, `
clock CLK48 (fall edge) 9.00 9.004 K! ^2 k" ~! y
clock network delay (ideal) 2.00 11.00
- c% F4 G8 {6 a4 T$ Q. j U_RST/nResetUSB_reg/CKB (DBFRBN) 0.00 11.00 f: Y+ a# p. g5 S' K' x8 f5 T/ m
U_RST/nResetUSB_reg/Q (DBFRBN) 1.27 12.27 r3 G& |. s4 p) U# i- L
U_RST/nResetUSB (ResetGen) 0.00 12.27 r
0 i( Q2 i4 E/ E' |, m+ p3 b A u_FUSB/RESETN (kFUS100_2m) 0.00 12.27 r
2 C+ x0 b( r. c( j' E9 a% t. C5 r u_FUSB/U132/O (BUF1) 0.32 12.59 r) m! m9 a& @. v5 {( S! H$ H
u_FUSB/FUS/RESET_INN (LFUS) 0.00 12.59 r5 X/ h0 d% t* g; w
u_FUSB/FUS/BIF/RESET_INN (LUSBIF) 0.00 12.59 r
& u7 d: s' p2 k# a u_FUSB/FUS/BIF/U42/O (BUF1) 0.33 12.92 r: h9 e) J& e& c& d3 Z) @+ v
u_FUSB/FUS/BIF/U49/O (AN2) 0.44 13.36 r6 L1 l1 B) g- @4 c
u_FUSB/FUS/BIF/U50/O (AN2) 0.64 14.00 r
( }! U' O+ B$ z; M- v' p u_FUSB/FUS/BIF/RESETN (LUSBIF) 0.00 14.00 r; |: v! P& C: m- w
u_FUSB/FUS/U44/O (BUF1) 0.69 14.69 r. m: e/ h! j# ]2 m. x# j
u_FUSB/FUS/LDSCR/RESETN (LDSCR) 0.00 14.69 r
2 q9 V; O$ L O# i2 _ u_FUSB/FUS/LDSCR/U85/O (INV1) 0.22 14.91 f
$ m) w( X M& ^2 [" c; V u_FUSB/FUS/LDSCR/U222/O (NR2) 0.46 15.37 r3 W# n4 C9 l4 p+ K6 A9 Z
u_FUSB/FUS/LDSCR/U8/O (AO12) 0.46 15.83 r
8 ~8 h ?$ w! a% L- X u_FUSB/FUS/LDSCR/U10/O (AN3) 0.50 16.33 r
5 i" ~& L8 f7 R$ a/ X$ H u_FUSB/FUS/LDSCR/U7/O (AO222) 0.51 16.84 r
7 b; x \; Z9 J, m7 O0 A4 x u_FUSB/FUS/LDSCR/U206/O (AN2) 0.36 17.21 r( j; i! b6 u2 Y; H7 X3 H
u_FUSB/FUS/LDSCR/epC/InterruptRD (LDSC_EPC) 0.00 17.21 r! g2 z7 S- l* L8 x7 L7 N" \/ t
u_FUSB/FUS/LDSCR/epC/U87/O (INV1) 0.12 17.33 f3 t2 |% e& d9 n# L7 h( |* A. g( |
u_FUSB/FUS/LDSCR/epC/U83/O (OR3B2) 0.34 17.66 f
% t4 g6 \7 F5 [2 r u_FUSB/FUS/LDSCR/epC/U82/O (NR2) 0.38 18.04 r
$ O1 {6 S. u% b u_FUSB/FUS/LDSCR/epC/U63/O (AO112) 0.50 18.54 r1 f. G; P9 r9 ]
u_FUSB/FUS/LDSCR/epC/D_epC[2] (LDSC_EPC) 0.00 18.54 r
7 L! s8 n9 Q/ d- ` u_FUSB/FUS/LDSCR/U158/O (ND2) 0.12 18.66 f' \5 V% y' {6 a7 @* Y
u_FUSB/FUS/LDSCR/U156/O (OR3B2) 0.19 18.84 r& `" e* M( q! J" a! i v6 e
u_FUSB/FUS/LDSCR/DD[2] (LDSCR) 0.00 18.84 r
6 |/ @6 r- h) `0 P9 I: G" e u_FUSB/FUS/MIS/DD[2] (LMISC) 0.00 18.84 r, i% J1 |; I+ Y7 J1 D
u_FUSB/FUS/MIS/U47/O (AO222) 0.36 19.21 r
6 `! u! L- N0 m u_FUSB/FUS/MIS/U45/O (OR2) 0.26 19.47 r
8 j; P. x: l# ?+ Z* @. |3 c u_FUSB/FUS/MIS/Q[2] (LMISC) 0.00 19.47 r
+ f( ^) Z, E. C, z u_FUSB/FUS/BIF/DOUT[2] (LUSBIF) 0.00 19.47 r3 e1 G) K/ t) Y
u_FUSB/FUS/BIF/U29/O (AO222) 0.32 19.79 r
8 n$ O/ J$ s5 ^! U' s* i) a9 D u_FUSB/FUS/BIF/PS/DIN[2] (LP2S) 0.00 19.79 r+ t% E5 S" M( Y8 J0 d3 ^
u_FUSB/FUS/BIF/PS/U6/O (AO222) 0.33 20.11 r: {! z7 _4 p" l% W y6 F
u_FUSB/FUS/BIF/PS/q_reg_2_/D (QDFFN) 0.00 20.11 r! |. W5 k! n' n( T
data arrival time 20.115 X( g1 a4 N$ m
) p% S$ W) y) x* I$ X/ t1 ~& |
clock CLK48 (rise edge) 18.00 18.00
/ K _# o, h X! J clock network delay (ideal) 2.00 20.00
" q& N) C# e' _& {8 W! ]# l9 T clock uncertainty -0.50 19.504 D# ?" k+ r/ J% X* j
u_FUSB/FUS/BIF/PS/q_reg_2_/CK (QDFFN) 0.00 19.50 r& I0 y5 Z2 T+ |
library setup time -0.25 19.252 q6 A8 t# J+ h/ k5 f8 |
data required time 19.25
, T& ]( n4 N0 f2 Q --------------------------------------------------------------------------
( @; d9 o6 c. ^% I K( x: d& | data required time 19.25
3 S& \0 }7 w" L5 h. { G data arrival time -20.115 q/ Y3 _) u a t8 i. A: t8 o
--------------------------------------------------------------------------3 G* s9 Q4 Q! K' U
slack (VIOLATED) -0.86% K4 s+ I- l7 w; W3 T
7 f. O! k3 y( V$ z: N3 \$ v7 W0 D
請問該如何調整使他met呢?? |
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