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Startpoint: U_RST/nResetUSB_reg
8 X- U! {# v* p/ G8 e (falling edge-triggered flip-flop clocked by CLK48)
; A0 K% z3 @ \ Endpoint: u_FUSB/FUS/BIF/PS/q_reg_2_% U2 _$ F9 |3 O6 ~
(rising edge-triggered flip-flop clocked by CLK48)
i5 y- m' A* ~9 s8 w0 Z Path Group: CLK48
( @ X' v' i& O' x! v Path Type: max
" D9 o5 ?3 L+ M7 b& H4 a& u, [# s
% |; Z4 _+ [1 R7 J& t3 G! | Point Incr Path
, ]/ B: Y% A& n8 I7 } --------------------------------------------------------------------------9 N" g- D* r4 h3 ~
clock CLK48 (fall edge) 9.00 9.00: x1 ?" p: I& o+ S8 Q, H4 u
clock network delay (ideal) 2.00 11.00/ C4 P% X4 F$ L9 r0 p V
U_RST/nResetUSB_reg/CKB (DBFRBN) 0.00 11.00 f% B; F# y8 ^( J
U_RST/nResetUSB_reg/Q (DBFRBN) 1.27 12.27 r
/ k4 d6 t) }; Q8 G% ? U_RST/nResetUSB (ResetGen) 0.00 12.27 r$ ^& H7 S! g8 W" }. ?; S5 o
u_FUSB/RESETN (kFUS100_2m) 0.00 12.27 r
- q9 Q$ p5 P% U+ E7 l u_FUSB/U132/O (BUF1) 0.32 12.59 r
& u) N% b1 `9 z u_FUSB/FUS/RESET_INN (LFUS) 0.00 12.59 r
( J' L) T- I: G7 Q u_FUSB/FUS/BIF/RESET_INN (LUSBIF) 0.00 12.59 r5 M1 X0 J+ _2 l: l3 Z. N* w
u_FUSB/FUS/BIF/U42/O (BUF1) 0.33 12.92 r- R3 U6 ]0 M2 _: s* S
u_FUSB/FUS/BIF/U49/O (AN2) 0.44 13.36 r5 ]) q3 r* F5 r5 ^ H) i- @
u_FUSB/FUS/BIF/U50/O (AN2) 0.64 14.00 r
" W/ I% j, `$ c4 O( c1 r u_FUSB/FUS/BIF/RESETN (LUSBIF) 0.00 14.00 r- H- I" S( e2 ~
u_FUSB/FUS/U44/O (BUF1) 0.69 14.69 r, g- ]5 b" x# l4 x
u_FUSB/FUS/LDSCR/RESETN (LDSCR) 0.00 14.69 r
3 v3 }: [ X9 {" @9 J1 _ u_FUSB/FUS/LDSCR/U85/O (INV1) 0.22 14.91 f, n8 J, e, w. w$ E
u_FUSB/FUS/LDSCR/U222/O (NR2) 0.46 15.37 r
. P- X1 E7 E3 I/ q u_FUSB/FUS/LDSCR/U8/O (AO12) 0.46 15.83 r
7 k( E! }8 [- r' g: Y( V" e u_FUSB/FUS/LDSCR/U10/O (AN3) 0.50 16.33 r4 g0 f5 I4 N" n. r
u_FUSB/FUS/LDSCR/U7/O (AO222) 0.51 16.84 r
0 [' m+ S# N/ [) ]: f: G; p u_FUSB/FUS/LDSCR/U206/O (AN2) 0.36 17.21 r
3 y. c1 z, { B& l u_FUSB/FUS/LDSCR/epC/InterruptRD (LDSC_EPC) 0.00 17.21 r
) L" o) j3 g" @+ L u_FUSB/FUS/LDSCR/epC/U87/O (INV1) 0.12 17.33 f9 c3 Z. {! S3 _7 |9 l2 C( `' X
u_FUSB/FUS/LDSCR/epC/U83/O (OR3B2) 0.34 17.66 f
. M7 [7 ~3 [ R) |6 o1 U u_FUSB/FUS/LDSCR/epC/U82/O (NR2) 0.38 18.04 r V0 ]$ v9 E3 p1 _
u_FUSB/FUS/LDSCR/epC/U63/O (AO112) 0.50 18.54 r7 u. F" j8 F* F9 P/ `3 K
u_FUSB/FUS/LDSCR/epC/D_epC[2] (LDSC_EPC) 0.00 18.54 r
# q" }& r8 o5 @0 h3 j2 [ u_FUSB/FUS/LDSCR/U158/O (ND2) 0.12 18.66 f S' ]1 g9 m& g1 ~
u_FUSB/FUS/LDSCR/U156/O (OR3B2) 0.19 18.84 r( w8 d; X% l; A8 C' N
u_FUSB/FUS/LDSCR/DD[2] (LDSCR) 0.00 18.84 r8 V5 A( T, f4 R# B4 r) V2 I- P9 K' t
u_FUSB/FUS/MIS/DD[2] (LMISC) 0.00 18.84 r
9 h; W1 C ~( X8 X8 w/ n( {" }5 B u_FUSB/FUS/MIS/U47/O (AO222) 0.36 19.21 r, i) D& w! t) Y8 Q$ N" M
u_FUSB/FUS/MIS/U45/O (OR2) 0.26 19.47 r
' r1 ^0 |/ P% s H u_FUSB/FUS/MIS/Q[2] (LMISC) 0.00 19.47 r, L/ L# `7 k% a; U9 z% H" @. u, @
u_FUSB/FUS/BIF/DOUT[2] (LUSBIF) 0.00 19.47 r1 p2 h# Q% D& D5 G
u_FUSB/FUS/BIF/U29/O (AO222) 0.32 19.79 r x4 v/ ~ J! U/ p. T7 l# @; X
u_FUSB/FUS/BIF/PS/DIN[2] (LP2S) 0.00 19.79 r9 F+ ^4 C3 L1 j. z
u_FUSB/FUS/BIF/PS/U6/O (AO222) 0.33 20.11 r
4 M/ s" ]+ X! ]9 d) d8 q u_FUSB/FUS/BIF/PS/q_reg_2_/D (QDFFN) 0.00 20.11 r& }# B [1 ?# U
data arrival time 20.11$ m% h+ F" x( A9 V% ~ @
0 f: I% C4 b- H7 _ clock CLK48 (rise edge) 18.00 18.00
2 z/ p% q! [- I3 W, x$ e7 c, P1 k, H clock network delay (ideal) 2.00 20.00* L$ ]0 e4 s, }, }# n* j( W
clock uncertainty -0.50 19.50% p S7 m! j$ ]) p n
u_FUSB/FUS/BIF/PS/q_reg_2_/CK (QDFFN) 0.00 19.50 r
$ j' n$ n X' [" i; q5 { library setup time -0.25 19.25
' d6 q# z- S$ L8 A, B& C/ \ data required time 19.25
" z o y+ ]1 A( M% M! n6 G --------------------------------------------------------------------------; p8 ]3 q& V4 N: o2 I9 ]
data required time 19.256 d- \, u, ^4 L! s( t
data arrival time -20.11
$ F: U, x# L3 E' R --------------------------------------------------------------------------
/ z4 U# K% E: m s- N slack (VIOLATED) -0.860 F1 Q% n' K2 G' N7 P
) n* n4 g5 O' V2 h/ D2 |) r! x6 `1 t. R1 j4 L! a
請問該如何調整使他met呢?? |
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發表於 2007-12-24 09:53:47
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