關於undersampling ADC的問題

jeffsky

設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

jeffsky

原帖由 jeffsky 於 2007-11-8 02:07 PM 發表
% P* ?0 P" [" p7 w" u5 K* B設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
' H0 I. B) W9 D4 \或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？/

DennyT

17MHz 的 tone 會不會是系統OSC or XTAL 的 16.667MHz clock feedthrough noise?

  J3 p7 M6 f% s$ u" L3 G: J因為即使是under sampling, alias image in first order term: (FS=54MHz, Ft=44MHz, Nyquist band=27MHz)
FS-Ft=54-44=10MHz
  \4 v0 _( D6 Q; G: h& U5 GFS+Ft=54+44=98MHz (folding 回 Nyquist band=10MHz)

2nd order term:
2FS-Ft=108-44=64MHz (folding 回 Nyquist band=10MHz)
, z8 N! Y4 Y. o/ f$ A0 {2FS+Ft=108+44=152MHz (folding 回 Nyquist band=10MHz)
( d- T5 ^: E6 @1 e: m9 g6 v|FS-2Ft|=54-88=34MHz (folding 回 Nyquist band=20MHz)
9 J" Q2 U5 H2 u# `7 UFS+2Ft=54+88=142MHz (folding 回 Nyquist band=20MHz)
- ~8 l/ }6 y( J: ?1 f' b+ b
2nd~7th Harmonic:
2nd = 20MHz
% }8 d+ L4 M$ ^# d5 x3rd = 30MHz  (folding 回 Nyquist band=24MHz)
4th = 40MHz  (folding 回 Nyquist band=14MHz)
5th = 50MHz  (folding 回 Nyquist band=4MHz)
) M6 ~6 @# m4 w/ w6th = 60MHz  (folding 回 Nyquist band=6MHz)
6 {0 r3 k: B( j; S, r7th = 70MHz  (folding 回 Nyquist band=16MHz)
你附的Frequency domain plot 在6th之後已在noise floor之下了, 故之後的harmonic可略去不計,
) T2 v4 M2 O3 B! h但是就是沒有17MHz的theoretical noise source.
  Y( J3 r9 ?, u8 P: h9 [來個Maxim AN928 anti-aliasing filter的文件:

6 [7 }- K9 X0 A# _; h4 _2 {[ 本帖最後由 DennyT 於 2007-11-10 12:00 AM 編輯 ]

jeffsky

Thank you for your kind reply.
5 ]2 [; F% v% v0 Q- U/ u; r1 }; UI have ever seen a paper or something else to say that when the signal frequency approaches the sample rate, the beat frequency is easy to appear at Fsig-Fs/2, for example, this frequency is 17MHz. It is as if sampling frequency is 27MHz. It is really a puzzle.

DennyT

有此一說:
當Fin接近於Fs/2時, ADC sample的電壓slew at full scale, 此時奇數點之間的壓差其實很小 (偶數點亦同), 但是相鄰兩點間的壓差卻很大, 測試上又稱為ADC envelope test, 而在此測試中被引進來的 "beat frequency" 會被視為noise, 使SNR下降.

. w. B; m% D. h; k' }也就是說, 若ADC內front end的PGA or buffer Amp slew rate不足, 此缺陷便很容易在此測試中被突顯出來.

就系統面而言, 拉高ADC的AVDD看看有沒有救, (ADC PAD_VDD反而要調低, 除了降EMI外也可拉低系統noise floor).
3 z  n  o1 s- y/ B
[ 本帖最後由 DennyT 於 2007-11-12 10:29 PM 編輯 ]

jeffsky

I am really thankful to DennyT's reply, it is a reasonable and constructive explanation on this issue. I will try to pull higher supply voltage to see if it can be relieved or removed or not. Thank you very much.