verilog 觸發問題

peliuya

今我欲使 sys_signal 此輸入訊號在正緣時，使 rst_B1 訊號為 High。

正緣過後（即下一個 system clk(50 MHz)），rst_B1 復歸為 Low。
4 N) s* s0 R% P
sys_signal 此訊號為  60 Hz , Duty ratio 為 50 ％ 的方波
* U& x' G1 C: T2 U- X9 j3 b
請問應該如何撰寫此段程式？

nesty.tseng

always @(posedge CLK_50M or negedge PORB)
begin
  if(!PORB)
# r  ]% ^: |4 K    sys_signal_d1 <= #1 1b'0;
  else
    sys_signal_d1 <= #1 sys_signal;
$ V9 X' U% D6 H- T3 {end

7 o9 O# Y$ ?, z& Y- u5 z5 Tassign sys_signal_pul = sys_signal & ! sys_signal_d1;

always @(posedge sys_signal or negedge sys_signal_pul)
- Y$ j) X6 `! W" X3 jbegin
- h8 d- i' y- x% p* u6 T. c: f  if(!sys_signal_pul)
    rst_B1 <= #1 1'b0;
4 Z' g9 E2 F" |* y! K9 }  else
( a! ]6 ]- A1 o& ?6 I/ r: {) e    rst_B1 <= #1 1'b1;
# K: [; A. S+ Y3 C3 jend