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CMOS Transistor Layout
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' w4 F& V) X& b! _" u3 W8 }Copyright © 2005
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0 R: I' Y u9 {( m5 p! qTable of Contents
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- M: t0 e) P1 n) I! y, HPreface
0 K5 R! A5 b: D5 @- c; V1. Introduction .................................................................. 18 A0 }# n+ {% b0 y) r+ ?! ?* p) L
2. MOS Transistors ........................................................... 2
" t2 t3 ?- m" z- ?- Q3. Fabrication of MOS Transistor ..................................... 5
9 n& y! i5 z& z: I4. Layout a Single Transistor .......................................... 11
2 G a8 V8 l, C: x# s1 BFirst Stroke The basic transistor layout ..................... 12
, t; x _$ y4 Y# {$ \$ ZSecond Stroke Compact the transistor layout ................ 13
0 S) g7 \ e2 v' ^Third Stroke Speed up the transistor ........................... 17
- b) a" K& |, l% Z& s5 x3 w ]3 e1 DFourth Stroke Clean up the substrate Disturbances ...... 201 J, B, n: J. N- C* b
Fifth Stroke Balancing area, speed and noise ............ 26
: S3 r9 Y( s" O) J; o2 L* VSixth Stroke Relief the stress ...................................... 29' f1 _( Z# O/ N) h$ W
Seventh Stroke Protect the gate ...................................... 30
# R5 w+ |- Y6 ~# m' c1 [9 [Eighth Stroke Improve yield ..........................................32" q: ?' f4 {7 d% l4 F6 J# {
5. Layout Several Transistors ......................................... 342 Q; R# N; X* t/ ~1 W; j, d
Eighth Stroke Improve yield...........................................35+ x# P5 p6 W# y9 H. \# n( {
Re-visit
- B% c; u/ S S% S! dNinth Stroke Close proximity .......................................36
& H# W2 G) Q& `" P1 [Tenth Stroke Interdigitated layout ............................... 36$ J/ k7 z7 w* A+ M R
Eleventh Stroke Dummy transistor ................................... 41$ m. M3 L B. E) N
Twelfth Stroke Two-dimension interdigitated layout ..... 435 h9 k h0 w" a$ y4 T- t
Thirteenth Stroke Guard ring for the matched transistors ... 45" `' G' F+ [. A
Fourteenth Stroke Keep NMOS away from N-well ............ 456 ?3 V V5 O- `% U( [9 j
Fifteenth Stroke Orientate the transistor ........................... 46
# u7 S6 N# A! _, g$ o2 {3 d/ R zSixteenth Stroke Match the interconnects ......................... 47
2 E1 p: M2 I) j3 j% xSeventeenth Stroke The unmatchable .................................... 50
2 r& n' ^# G- W6. Verifying the Transistor Layout ................................. 52
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1 A( @; ]# v: f) `: y3 _; g# m[ 本帖最後由 semico_ljj 於 2008-11-1 04:01 PM 編輯 ] |
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