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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題
% \! z3 o, A4 k& z( D0 V7 n' i8 V
4 V; V  d9 e( ~; V; F請教業界各位先進/ T6 [7 @% `0 [8 \
目前的chip開發,需要多少投資?( W) H* c3 f3 _% [1 k, W
首先是假設 Febless design house.
! C; C+ B) t: X8 B自家由algorithm 到 RTL simulation 完成1 ^2 S6 M- o2 m& K
後端包給 backend service 公司 (layout, mask, Fab, assembly..)
# F9 D6 {! ?( `& F  m以 ARM9 or ARM11, AMBA2.0 為platform
, _+ y/ z, u; \: H那麼
8 h# V. W. _6 \. X+ l% a- V8 f  (1)90奈米, NRE大概多少?
# b( y$ e$ C4 d0 o$ P/ J  (2)65奈米, NRE大概多少?
, q1 Q' W9 a+ {/ n+ N2 E2 @- V# s  (3)或是您知道其他製程, NRE大約多少...3 P( E3 I# z& O8 n7 c& r' i' U+ _
5 J* J" k% I; I) h2 {
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?; F5 k. u  `7 m( y( A9 P0 X" q
How many mask layers it will be?
' l0 T( o% V6 C7 u6 c5 s4 J, p! N! ^Besides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?
. y; F* v+ W% S* DHow many chips you need? A full set mask or MPW?+ P/ @: ]/ V. X+ i: {' ^
What package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,
) c6 ?& P: U$ b4 v( k6 k
0 C2 u- F, v; oI just estimate the investiment of a ASIC team.: c! l) Y  m5 C  c
not servey for a project." e+ Z: L* t0 A% Z/ j- w
So, I just want to know the range of NRE.5 n* B" \) ~3 Z5 x- d
  B( o' \" w& Q% y
For example, It will be . h- Y, S% O1 i+ N
(1) 5,000,000 NT$ ?
+ E* }6 |3 B$ w3 ~8 n(2) 8,000,000 NT$ ?4 Z* c+ P9 f7 k' @
(3)10,000,000 NT$ ?
* p) [' v7 B! g4 I7 G0 v(4)12,000,000 NT$ ?
+ r' T8 w& X( h2 ?1 v9 n(5)15,000,000 NT$ ?- H# A  R# @5 X4 n' ]3 p8 E

% h% T5 u6 X* r( N' v! Y2 F# USure, I understand following things:
5 G; I' z! N2 o( u3 O# z" U5 y - full set mask cost more
5 k' U2 G6 w0 ? - PLL/LVDS... analog IP are extra cost
- z! R2 b$ r/ _. E8 O5 s" { - pin-count and area also influence cost6 J4 C; Y% U; O( n; F! V
- different package also cost different6 g7 u; q5 Z  u! L0 r1 }1 o
& }8 X2 A5 H5 ^, y! ?( Y2 m6 R
Therefore, if really need information for estimate,: q2 ]5 s0 @; E, Y* Z
just for example.& B# u# v0 O- v1 q3 J8 H
Let's assume a SoC for FullHD TV application! p# E' b1 a3 |/ w3 w# E& Z
it will include' f+ l- {, R' Y3 }: C- q
  - ARM AMBA( |+ @1 d" \, D. [
  - DDR2 I/F
2 _  H4 C' l, s7 \1 h& U  - GPIO, IIC,...
' }: X+ j7 M2 y" R7 I: D- \  - LVDS out (dual link)
% P8 R8 {  Q0 J( ^# x# K  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,( k- U1 t8 c, W4 Z6 V; J/ J
  - 12bit ADC, 10bot ADC x2
% @9 ]/ Y' o9 i" w  - PLL/DLL
3 f( g5 e. Z2 a4 {. b. r  - 256 pins 以上
3 g' f+ ^9 r+ Y
. O  P0 X, H& Y' R8 N' h8 R; wThan,... any idea about NRE fee?
' V$ M3 n7 i: ^' ]1 oagain, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,
; G: L/ e2 T: Xbasically 65nm-->USD$1M above and 90nm-->700K above9 i$ ]" M2 P& x- Z2 Z1 k' ?+ G
and base on different foundry has difference price!
7 D0 L4 g0 n8 u5 j; Q" f6 Nthis price did not include any specific IP like TV encoder, decoder, vedio codec....
  c9 ~0 J4 r& X1 q- M% S3 A3 ?$ h/ oand did not include the ARM licensee...9 x" W- V9 e) u8 f( b/ R/ i* X
actually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)
/ o; ]% F+ i& y4 F1 z1 Y! x1 Dand package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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