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Layout Guidelines for Optimized ESD Protection Diodes- O* m& A* N, }8 {9 H
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Karan Bhatia and Elyse Rosenbaum
- _+ H" m; M- M+ {" PDepartment of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign* `$ i( ~& O! S/ F; p, v$ L
1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu
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Abstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are4 f( N0 y# R9 t! o" X9 c. p
investigated. The current compression point (ICP) is introduced to define the maximum current handling/ f0 d* ~; n+ h) w" B$ u, B8 c9 `* j
capability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the4 J6 i) i* x: D; u" g) s
performance of the structures investigated herein. |
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