關於cell-based 流程的DRC問題

ywchywch

請問各位大大
我用TSMC18的design kit作cell-based layout的練習，軟體是用encounter，大部分的步驟是依照CIC所提供的Lab去做，完成之後用我的GDS檔去做DRC，會出現下列的DRC ERROR，而且是M1~M5、via1~via5都會有這方面的error，因為error的數目頗大，不太可能用人工去debug，所以我想請問有經驗的大大們，能不能告訴我最大的問題點在哪裡？以及這些錯誤代表什麼？要如何debug比較適合？
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$ C5 m6 I" |; H先謝謝各位大大了!!感激不盡!!

1. M2.W.1 { @ M2 width < 0.28
% Y8 g* O2 ~9 {. W  H5 h. G/ W9 H  INT M2 < 0.28 SINGULAR REGION ABUT < 90
}
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. d7 I9 R+ o3 y5 u+ ~, |2. M2.S.1 { @ M2 spacing < 0.28
  EXT M2 < 0.28 ABUT < 90 SINGULAR REGION
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3. M2.S.2 { @ Wide M2 (>10um) min. to M2 < 0.6 um
  M2_S5 = SHRINK (SHRINK (SHRINK (SHRINK M2 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5
  M2_G5 = GROW (GROW (GROW (GROW M2_S5 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5
1 C* C  \" r; o" I  M2_Wide = M2_G5 AND M2
; Y  L7 C4 b9 X
  M2_Exp = SIZE M2_Wide BY 1 INSIDE OF M2 STEP 0.196
  M2_Branch = M2_Exp NOT M2_Wide
3 \  ?) `. q+ E" ~" r7 n# U& J  M2_Branch_edge = M2_Branch COIN INSIDE EDGE M2
% j% p. V6 S$ ~$ f5 V/ Z) X9 }  M2_Check = M2 AND (SIZE M2_Exp BY 0.6)
  M2_Else = M2_Check NOT INTERACT M2_Exp
( ?$ d" X' F1 ?/ P  L/ {. N  M2_Extend = M2_Check NOT M2_Exp
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  EXT M2_Wide M2_Else < 0.6 ABUT >0 <89.5 REGION
, |, }/ L0 t% P  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 OPPOSITE REGION
! B; i  J0 C; u, q* N7 J: w, B- I  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 CORNER REGION
  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 PROJ==0 REGION
  A = EXT M2_Exp < 0.6 ABUT > 0 < 89.5 SPACE REGION
  A NOT INTERACT M2_Extend
}
) r' z9 d8 E4 w- M- j4. M2.E.1 { @ Min extension of a M2 region beyond a VIA1 region is 0.01 um
9 X* w. }3 L, R* V( @   ENC VIA1 M2 < 0.01 ABUT<90 SINGULAR
   VIA1 NOT M2   
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# Z. K" [4 l' k5. M2.E.2 { @ Min extension of M2 end-of-line region beyond VIA1 region is 0.06um
   X = ENC [VIA1] M2 < 0.06 ABUT < 90 OPPOSITE                // a narrow side
& ]$ ?0 [! e- i+ C# a; e( v9 ]2 a- u   INT X < 0.26 ABUT == 90 INTERSECTING ONLY       // adjacent narrow sides
! H: k0 e* t3 w: Z  M2 U/ D! j}

6. M2.A.1{ @ Min M2 area region < 0.202
  AREA M2 < 0.202
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# A# f& K4 _8 u" E2 W// Density check M2.R.1 included at the end of this file
// VIA2 checks
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7. VIA2.W.1 { @ VIA2 must be 0.26 x 0.26 um
3 S9 h1 \" v1 M" K' z  A = NOT RECTANGLE VIA2 == 0.26 BY == 0.26 ORTHOGONAL ONLY
  A OUTSIDE RNGX   // exclude from metal fuse protection ring area
}
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8. VIA2.S.1 { @ VIA2 SPACING < 0.26
  EXT VIA2 < 0.26 ABUT < 90 SINGULAR REGION
}

9. VIA2.E.1 { @ Min extension of a M2 region beyond a VIA2 region is 0.01 um
6 Z/ F5 E  q4 ~% ^! c3 k" }$ |  ENC VIA2 M2 < 0.01 ABUT<90 SINGULAR
  VIA2 NOT M2   
}
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5 t3 q4 }+ g) q# E9 G5 e10. VIA2.E.2 { @ Min extension of M2 end-of-line region beyond VIA2 region is 0.06 um
   X = ENC [VIA2] M2 < 0.06 ABUT < 90 OPPOSITE         // a narrow side
   INT X < 0.26  ABUT == 90 INTERSECTING ONLY     // adjacent narrow sides
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motofatfat

我猜你試用APR軟體RUN出來ㄉ
應該是相同NET ㄉMetal space 和 via extension
不夠的問題,通常會用 skill file 來修正

michael6172

我覺得你打電話去CIC問工程師會比較快吧 ...