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AMD Geode LX 800@0.9W處理器
General Features9 R0 r- g% _& [( l c6 C6 V
■ Functional blocks include:
5 ]$ V: Q, i* d/ t+ k7 W# n! J— CPU Core) K" y' ~; P8 p4 l% K5 P! M6 K
— GeodeLink™ Control Processor4 m; V7 ?+ `: _0 h9 t( r5 i
— GeodeLink Interface Units
# R+ [* S- ~+ L% r! B' A$ ~— GeodeLink Memory Controller
) A* Y+ U3 y* u$ ^0 w7 n— Graphics Processor6 g, e, R; v4 L! c4 `) M. D7 m
— Display Controller
# S6 }$ I( \( q+ m. v3 p. V& O3 _! Z— Video Processor
]) j' ^$ k! b2 E6 Q7 @– TFT Controller/Video Output Port
* V& K% z% r! W& E7 p— Video Input Port y& E! c2 Y! a9 @( n, H, w! Y
— GeodeLink PCI Bridge( y5 P1 J6 I% f. B, G+ D& f+ c. A
— Security Block
7 J0 N9 P6 e7 T# g■ 0.13 micron process
2 d" d5 g8 |2 H■ Packaging:
/ u* M3 F2 Q2 a# U/ \— 481-Terminal BGU (Ball Grid Array Cavity Up) with
1 W/ c( f8 n/ B% Yinternal heatspreader# T) B: ~; `8 [+ ~, `
■ Single packaging option supports all features5 i9 \6 r3 C' |( W# T9 ?1 |& F! x
CPU Processor Features
, X* ]/ Y8 L6 O1 f4 ]■ x86/x87-compatible CPU core
' [ u. l, A+ ?; v# B( v■ Performance:/ H& s; O/ X# J
— Processor frequency: up to 500 MHz% ?, V; H6 h$ x+ m
— Dhrystone 2.1 MIPs: 150 to 450; \+ ~% T1 Q3 Q% k5 z
— Fully pipelined FPU8 r/ H! b# k. w$ d0 R9 t# z& o
■ Split I/D cache/TLB (Translation Look-aside Buffer):
8 q( {$ ^5 O1 H0 l; Y— 64 KB I-cache/64 KB D-cache& |4 o% \7 U; w+ M( `$ n3 L$ o
— 128 KB L2 cache configurable as I-cache, D-cache,
7 F7 t' s C6 U# ~- x. ^" @. uor both
# _1 N" X! }( D' \+ y* o1 v■ Efficient prefetch and branch prediction: q/ \ w) Y0 I
■ Integrated FPU that supports the MMX® and/ P% y$ ?$ l& A; U2 X; S
AMD 3DNow!™ instruction sets
M9 w7 {! o" Y/ w1 g& x B$ g. G■ Fully pipelined single precision FPU hardware with
" m9 S* y" F6 H5 d. m F, Q/ C+ |microcode support for higher precisions+ a& T. }4 [0 T4 H/ w' p
GeodeLink™ Control Processor. J0 m* n8 [9 l% w- \4 N
■ JTAG interface:
0 f0 ^2 X3 A& z% \+ y$ W/ ^— ATPG, Full Scan, BIST on all arrays
( I. \( q& y( @( V' b( F3 Q" C6 |— 1149.1 Boundary Scan compliant
. @: g5 {- c& u! B■ ICE (in-circuit emulator) interface) I4 X' d& f7 {( C
■ Reset and clock control
( ^& b- l- B( b7 O( k9 `0 O■ Designed for improved software debug methods and
. m5 I% o1 O& q2 a% L q' h4 pperformance analysis
7 d) o1 M- a7 M' I/ R' z' P■ Power Management:
% B3 p) w" s# R. Q$ x& D5 z3 m— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
0 f, P, b4 p! L( {* Z500 MHz max power
! R! p0 W1 E6 l# I7 `8 A8 G— GeodeLink active hardware power management
2 i) y+ C* g) W* L7 y7 M+ r— Hardware support for standard ACPI software power4 J4 l% ?9 v- z3 n
management5 @' ]0 t3 f' o; f+ C% f
— I/O companion SUSP/SUSPA power controls
$ v7 V8 K9 U* _! _— Lower power I/O
& A3 I9 Y: `5 `( L— Wakeup on SMI/INTR
; i1 |/ \ k! \! g■ Designed to work in conjunction with the
2 O. I" ]3 H' Q9 F; R2 XAMD Geode™ CS5536 companion device
( v/ w6 f- y1 N6 S0 ]GeodeLink™ Architecture
4 L. i) `! u$ @9 f5 h+ i% O/ P■ High bandwidth packetized uni-directional bus for
8 L X# ]' N! [5 kinternal peripherals* i: s" A8 ?1 O5 z4 W7 ]# p5 W
■ Standardized protocol to allow variants of products to be
* J3 R8 }- D7 ~; | xdeveloped by adding or removing modules
0 d! v0 E+ g, f6 h, B; `5 A2 L■ GeodeLink Control Processor (GLCP) for diagnostics$ k) G1 d F( d. d$ m
and scan control! \+ N/ }+ C" c( y4 F( d; y# Z9 J3 x; {" g
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
4 d# P, C. I- Q, I8 A# [' JGeodeLink™ Memory Controller& v+ L z+ b7 v5 R) f* I L
■ Integrated memory controller for low latency to CPU and
4 ?& n& u5 c# y+ a2 Qon-chip peripherals' H( p( z. ~! g& |/ P( n) b. b
■ 64-bit wide DDR SDRAM bus operating frequency:% n- i# t% S; ~( ]" |- O; X
— 200 MHz, 400 MT/S1 A. E8 j. N. O% i6 p, h4 g
■ Supports unbuffered DDR DIMMS using up to 1 GB
1 ]$ d. h$ k+ ^4 r" Y; B; T3 E0 w6 v# ^DRAM technology/ d1 `% g8 [/ H
■ Supports up to 2 DIMMS (16 devices max)" K( y, B3 ?; y8 p* l9 C
2D Graphics Processor
& h! w4 |; I2 Q) Y1 i+ L# y■ High performance 2D graphics controller
- F4 L& T' H6 a" G. V: A■ Alpha BLT9 I! p- l/ m# W# M0 d7 `) B
■ Microsoft® Windows® GDI GUI acceleration:' y( g* ]6 X1 `, f7 M1 c
— Hardware support for all Microsoft RDP codes
1 y, @$ k4 r: E" Z3 R■ Command buffer interface for asynchronous BLTs
6 L- p8 _; n2 K4 |# L2 u■ Second pattern channel support; [7 V6 i" j4 b, X6 W- I) w/ o
■ Hardware screen rotation |
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