Circuit and Layout Co-Design for ESD Protection in BCD

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Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
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Wen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE

; z" @; U6 x' \) s* [2 v: y' z- nAbstract—The n-channel lateral double-diffused metal–oxide–
/ A1 d1 }* F4 @. J1 fsemiconductor (nLDMOS) devices in high-voltage (HV) technologies
4 }1 t6 S; L0 zare known to have poor electrostatic discharge (ESD)
robustness. To improve the ESD robustness of nLDMOS, a co-design
3 z1 N; d" M" b5 U* k2 h0 Lmethod combining a new waffle layout structure and a trigger
; t9 J" a- g( N. Kcircuit is proposed to fulfill the body current injection technique
3 U8 \% [! }3 N. B. w% rin this work. The proposed layout and circuit co-design method
& z( p# ?. y2 B6 y7 Pon HV nLDMOS has successfully been verified in a 0.5- m 16-V
  P6 F5 r4 G8 f0 |bipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
process without using additional process modification. Experimental
results through transmission line pulse measurement
7 [$ u/ H1 n) H7 ?2 v- s/ N$ r* n: aand failure analyses have shown that the proposed body current
injection technique can significantly improve the ESD robustness
of HV nLDMOS.

: y. C- Y; d+ k# X6 U* H# b5 [1 PIndex Terms—Bipolar-CMOS-DMOS (BCD) process, body
) ]# H0 n6 O# x$ ycurrent injection, electrostatic discharge (ESD), lateral double-diffused
, V4 ?0 D5 X* c* [: |metal–oxide–semiconductor (LDMOS).

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