Berkeley的一篇博士论文_Jitter Reduction on High-Speed Clock Signals

hitxiaojun

This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter
Attenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
* L" g" K% [9 Q1 F4 p) Xon par with commercially available PLLs, while being relatively simple to design and use as
an on-chip solution. The main difference between the JAC and PLLs is that the JAC does
, q5 L# F+ [, y7 Jnot guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In
the following sections the effects of jitter, present methods to reduce jitter, and application
of the JAC will be discussed.

遊客，如果您要查看本帖隱藏內容請回復

satto0216

謝謝大大…dll&pll的任何相關資料我都很需要
希望可以幫到我，

liyao

剛好工作上碰到jitter measurement問題,下載參閱一下,感恩!!

liyao

> < 我很少上來 沒錢下載 怎麼辦呀!!

anita66

Wow, 新的耶?!真是太讚了, 先下來study看看, 有機會在跟大家分享心得, 3Q~

planet1114

最近在工作上一直被noise所困擾,
下來看看能不能從這有新的啟發.
先謝啦

godman

謝謝你的分享，希望會有所幫助。

b56389

多看看別人所推薦的paper
, m* t0 o" H1 g5 D' A研究其的看法與理論
相信對增進自己的實力有幫助的

donnie

Thanks for Sharing
7 Z5 d* M; y! y/ [3 aThanks for Sharing

donnie

Thanks for Sharing!
Thanks for Sharing!

ychchip

jitter is important issues in analog ic design.  it must be carefully designed including path match and high speed.

eceking

可惜沒足夠的錢幣............................................................!

anita66

感謝大大無私分享, 不知道有沒有跟Thomas Lee的論點是否相同??3Q~

xp212125o

thank you~
感謝分享
正好有需要

lyx1982

谢谢分享！收藏了！！！

starfish311

回復 1# hitxiaojun
: E# G- I$ F7 g8 S8 e3 C9 \, E
- y# J: Z: d+ x$ \; Z+ Y6 y
( {( P- w5 z: l* I* U+ {    謝謝你的分享，希望會有所幫助

ja1688888

剛好需要看PLL jitter 學習一下 感謝
. u. Q5 p% k# m5 @" w# W

alienwarejian

谢谢
3 B$ E+ X& f, x- L. I8 p4 S谢谢

microuser

感謝大大無私分享，剛好需要看PLL jitter 學習一下 感謝

microuser

感謝大大無私分享，剛好需要看PLL jitter 學習一下 感謝！