hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs
4 H8 X5 ~" S5 Y! U0 b; K$ q1 _
要怎麼定義用
9 {2 }, D4 }5 m' Y' z' E( nplot LX??
2 `8 [" X* x, l0 A
請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .
/ v* q8 O0 b& Y) w! P
2 E5 y1 |' A  y. qCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.


For your reference.

0918429587

CAB_BS    LX28
, A/ s7 ?" ~8 y- C& DCAB_BD   LX29

其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
這是 CGDBO  CGSBO CBGBO
% n. {0 ?# C3 l
& n" ]. H, b* {, ~+ U' r不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
An example for your reference...
4 V4 g7 Q# g; e: \
% `6 D3 u* I! h7 j. C----------------------------------------------------------------
***** Gate Capacitance Plots *****
.lib 'your_component_model' lib_corner
.temp operational_temp
' k0 u4 f4 M( A4 b.option dccap=1 post
6 M4 B2 n/ }. u1 ~  L2 [0 K8 l% sm1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
& i5 O( q& M9 T) ^- r9 Gvg n_gate gnd 5
8 y3 X4 Y0 \8 Qvb n_bulk gnd 0
+ Y2 c: }9 K; x/ ?1 @5 d.dc vd 0 5.0 0.1
/ _! J' y0 G! L& j5 S.print   CGG=lx18(m1)
; b/ d: N8 c% ~+        CGD=par('-lx19(m1)')
+        CGS=par('-lx20(m1)')
+ j3 s) E$ `2 a8 y9 j+        CDG=par('-lx32(m1)')
+ n7 N  z1 k0 ]& _% @. S1 v" ]; k2 v+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
.ends

----------------------------------------------------------------
Six capacitance are reported in the operating point printout
! p& ~% Y, H# q/ p* t& [    cd_total = dQD/dVD
    cg_total = dQG/dVG
2 A" v5 `2 K5 t2 m/ U' G5 f    cs_total = dQS/dVS
' S' B6 e; m: w    cb_total = dQB/dVB
    cgs = -dQG/dVS
    cgd = -dQG/dVD
There capcitances include gate-drain, gate-source, and gate-bulk
overlap capacitance, and drain-bulk and source-bulk diode capacitance.

1 p. P& V, V# b, g0 bCGG = dQg/dVG
7 i4 X5 @2 d! W6 m( J0 tCGD = -dQg/dVD
CDG = -dQD/dVG
6 T7 G" G  y% h5 s1 b
The MOS element template printouts for gate capacitance are LX18~LX23
! V; Q% ?$ L3 v; @and LX32~LX34.

( w& W( ?# s, G/ ?; QLX18(m) = dQG/dVGB = CGGBO
& r) C8 x' q) ^2 VLX19(m) = dQG/dVDB = CGDBO
LX20(m) = dQG/dVSB = CGSBO

LX21(m) = dQB/dVGB = CGGBO
: O  {9 J/ C+ i) r  F9 h5 G; V$ }" tLX22(m) = dQB/dVDB = CGGBO
LX23(m) = dQB/dVSB = CGGBO

LX32(m) = dQD/dVG = CDGBO
8 B9 \& ]8 j/ X& _  A1 M: ?LX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO

The equation shown above is for an NMOS with source-bulk grounded
configuration. Refer to the user's manual for more detail ^^