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Senior Digital Design Engineer
3 B$ S. A, K. [ [* u, e6 ~8 \; e8 `. `, S
公 司:A famous European IC company
1 h0 i) p% N* s5 f% M r6 z$ r8 ^工作地点:上海) M; R' A. K6 [ ]* ^
0 K3 G' j, Z3 u
Job description ' D D* z) y' @" b
- define system partitioning of s/c circuits and system / n9 ~( t# j1 c0 h& H
- define HW/SW co-partitioning & Q3 R7 P! Z+ |4 x( T
- provide technical feasibilities based on system simulation and/or FPGA based demonstrator
2 B4 |( f- V7 @) b9 F* {" B# y# C8 R- propose new technical solutions on s/c and system level
3 t: o; Y% I) T, \/ m) |- design digital part of mixed signal (smart power) ASICs ) C4 M/ K; U/ S5 ^
- close cooperation and interaction with international teams 4 x! K& a8 L" D9 y
- coach junior engineers . ~0 I8 I0 j( k
( u5 O" T# _4 @+ YRequired knowledge competencies and attributes 5 M% K* H( M* ^$ H1 y4 B5 ~# G8 L" N
- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent) " H) @2 S2 P1 W( q
- > 5ys experience in digital design : c5 t' F8 _7 h D) q: i9 ?" J9 Q% b
- good understanding of ASIC mixed signal flow (Cadence based) . f' F7 h% H7 A5 I4 r! G" e
- strong background in HDL coding, verification and toplevel integration % T. Y9 \! B6 a& t4 h- [6 v. y
- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray)
6 X. t- J# ]: r& [' Q ?8 X- experience in FPGA development
* w5 `$ r/ L6 o- very good communication skills (written, oral)
. |8 F. v% D+ q# w- self motivated and high level of flexibility
0 y X& ~4 H$ R+ u; L2 ]) o- foreign languages: English, German (not a must) |
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