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In order to save test device, usually will do Power to Ground then IO to Power/Ground and the last is Io to IO. c5 u* _. n$ |1 e: ]' W7 d5 y8 u. z
: X9 A; J$ _1 _, h) pThe reason is:
1 n0 Q1 f; B0 E/ l5 d! k1. If power to ground can not pass, the rest combination has less chance to pass
! }6 u: Z. `# {( F" p! C% n% }2. Usually power pin count is less than IO pin count. It is fast to get an idea how the chip's ESD level( s9 d) E, r6 D) {8 C& ]% g! v4 z
3. If failed, it's easy to find the failed ESD zapping combination |
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