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Verilog-2001 added the much acclaimed @* combinational sensitivity list. The primary intent of this enhancement
. `/ e, F9 X: o* r! lwas to create concise, error-free combinational always blocks. The @* basically means, "if Synopsys DC wants the& A5 ?& X- ?4 U$ Q% M# k5 p
combinational signal in the sensitivity list, so do we!"
7 ?6 q0 I! ~5 j% U+ EExample 1 and Example 2 show the Verilog-1995 and Verilog-2001 versions respectively of combinational) R H# n- L; u$ `" w. I
sensitivity lists for the combinational always block of any of the three always block fsm1 coding styles.
) G G5 n' y) l
9 q# W& n( O# B* Aalways @(state or go or ws)% m& x* X$ n/ y5 Y& s
begin
& h+ m& ?4 [& {, T" d' s9 Q" s! k7 F..." ~8 k/ @- j8 K v& A2 D( }
end" r" m9 C8 R s0 l" I
//Example 1
1 \9 S& ?9 G. e
1 h" ]( g/ p1 J! V1 z ], M# X& Z5 w$ i3 y1 K6 @7 d
always @*2 b7 |) n; G4 v6 z: T
begin# ?- _# I3 `: X; b& h! a
...& _6 ?; |% Q# {& M/ v
end
+ W8 `( d2 q/ s# w//Example 2
* y( ^, r# R" U7 F) d1 K) A& w
/ W( _* ?+ J) ]5 XThe @* combinational sensitivity list as defined in the IEEE Verilog-2001 Standard can be written with or without
3 n7 u) a+ B; u5 `2 s" R3 Z; Iparentheses and with or without spaces as shown in Example 3. Unfortunately (* is the token that is used to open
7 V( {* g6 o" `* M; m: pa Verilog-2001 attribute, so there is some debate about removing support for all but the always @* form of this4 ? U8 o0 e' F: w( W8 O8 v7 |; P
combinational sensitivity list. In-house tools would probably also be easier to write if the in-house tools did not2 f; U3 U& Y. G! i6 T) p- H1 B
have to parse anything but the most concise @* form. For these reasons, I recommend that users restrict their usage
. Z6 g& \+ v) ?6 R+ o/ ]* U F! V) nof the combinational sensitivity list to the @* form.
P" \) q+ l$ h; {always @*
, B2 p) \% C% jalways @ *
; C7 c2 Q; q" f4 K% talways @(*)
( g0 R3 V1 K# A/ I+ V% talways @ ( * )
1 ~' j! ~ M% d$ K//Example 3 |
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