Optimization on ESD Clamp Circuits in a 0.13-μm Technology

semico_ljj

Optimization on NMOS-Based Power-Rail ESD Clamp
9 Q% ?* j: W( O' j8 i# uCircuits with Gate-Driven Mechanism in a 0.13-μm
) l! v2 z& X4 A3 C! _$ rCMOS Technology
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Abstract—NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the
6 v- W7 O+ T+ Y  o- }8 T" Cdesired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.
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4 I! O' o$ }& x注意：内容有一定深度，初学者可能看起来有些困难。

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semico_ljj

IV. CONCLUSION
The designs with 3-stage-inverter and 1-stage-inverter
controlling circuits have been studied to verify the optimal
$ g2 j8 b" M, O3 @* ~6 L" adesign schemes in NMOS-based power-rail ESD clamp
4 u5 a+ O2 i2 F% `circuits. In addition, two ESD clamp NMOS transistors,
/ b6 _* s3 o9 k* Xhaving snapback and no snapback operations, also were codesigned
7 C3 Z7 v' i: {% j9 K' e7 z0 a4 pwith different controlling circuits to realize the
7 q. w3 t3 v' limpact on their required performance. According to the
experiments and analyses, the 3-stage inverters can slightly
increase the ESD robustness, but they also can dramatically
sacrifice the mis-trigger and latch-on immunity. The 1-stage
inverter should be an appropriate and reliable candidate for the
5 j" q% L7 r0 v0 x3 T& ]+ kpower-rail ESD clamp circuits.

aicder

very good!
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kevin5461

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layes2

還要回復啊。希望能學到一些東西，謝謝！

jstsai

very useful, Thanks for your sharing...........

chkd002

正在學這方面的知識，多謝分享好東西！