CMOS Transistor Layout

semico_ljj

CMOS Transistor Layout

" H( @: v; r9 |8 G3 Z/ l7 t, VCopyright © 2005
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# e, ~) v# V! L0 b2 `Table of Contents

7 i8 @) R1 r+ l: e0 FPreface
1. Introduction .................................................................. 1
. h* H) Z# {! G1 u( }  b2. MOS Transistors ........................................................... 2
3. Fabrication of MOS Transistor ..................................... 5
5 v& A6 D" x% e5 T3 |4. Layout a Single Transistor .......................................... 11
* w/ {# j7 b7 }& ?* w1 {. y# eFirst Stroke The basic transistor layout ..................... 12
Second Stroke Compact the transistor layout ................ 13
Third Stroke Speed up the transistor ........................... 17
3 x# q" }5 x6 y: q& W# L# O. zFourth Stroke Clean up the substrate Disturbances ...... 20
0 L) S: r9 Q* L; _1 p4 yFifth Stroke Balancing area, speed and noise ............ 26
Sixth Stroke Relief the stress ...................................... 29
Seventh Stroke Protect the gate ...................................... 30
Eighth Stroke Improve yield ..........................................32
5. Layout Several Transistors ......................................... 34
Eighth Stroke Improve yield...........................................35
Re-visit
0 X' ]  d1 V  T- Q! lNinth Stroke Close proximity .......................................36
2 t9 ^+ y: F% `, V4 JTenth Stroke Interdigitated layout ............................... 36
, B4 W% M% ]0 ?2 Z' I1 vEleventh Stroke Dummy transistor ................................... 41
$ `$ l! Z7 y. c9 pTwelfth Stroke Two-dimension interdigitated layout ..... 43
Thirteenth Stroke Guard ring for the matched transistors ... 45
/ R1 _' K' S: D6 ^Fourteenth Stroke Keep NMOS away from N-well ............ 45
Fifteenth Stroke Orientate the transistor ........................... 46
Sixteenth Stroke Match the interconnects ......................... 47
$ G8 D! l' N- s3 SSeventeenth Stroke The unmatchable .................................... 50
6. Verifying the Transistor Layout ................................. 52
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% b6 h1 n5 E/ s[ 本帖最後由 semico_ljj 於 2008-11-1 04:01 PM 編輯 ]

semico_ljj

这本书的下半部没有找到，不知哪位有的话可以共享！谢谢！

semico_ljj

Preface
Many IC design books emphasize on circuit design theories and there is
% p! o* n; M& Q0 a: L" N5 slittle coverage on custom circuit layout techniques. Hence this book is
specially written to focus on the custom circuit layout techniques. It is
an easy book for the custom layout engineer as prior knowledge on
circuit design is not necessarily required to understand the content of the
book.
$ b4 @# s4 O( [This book is written for two groups of audiences – New & Experienced
0 E3 O- g/ y' c. F2 b  _' K3 Jcustom layout designers. The new comer to custom layout would benefit
from the wider perspectives in implementing the design to a layout. The
experienced custom layout designers, on the other hand, will have a
8 @- e/ Z* Z7 ebetter appreciation of the rationale behind the layout practices.

semico_ljj

这本书Layout基础知识讲的很不错的，可以好好研读一番！

meis

請問一下 " CMOS_Transistor_Layout_KungFu.part2.rar "   為什麼 ? 這個檔 無法下載ㄋ

meis

請問一下 " CMOS_Transistor_Layout_KungFu.part2.rar "   為什麼 ? 這個檔 無法下載ㄋ
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7 d  m* S  U- L! B! N) C( ~下載解開 為 0K  可否告知在那兒還可知 part2 data ,  謝謝 !!

meis

我已下載  " CMOS_Transistor_Layout_KungFu.part2.rar "  但是 解壓縮 候   0k  沒有內容  , 請作者補上內容  ,   感恩  !!

ychchip

Sound good although the material is not whole part.  It is helpful in beginer of ic layout.
I appreciate that the author and the poster contribute the material .....