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CMOS Transistor Layout) @3 G+ Q2 Z& k$ x! t
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Copyright © 2005
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8 c( I$ I8 I* K" xTable of Contents
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Preface: E2 L9 K1 L* m; P' q7 J0 e [
1. Introduction .................................................................. 11 C) L- y# ~2 f( v
2. MOS Transistors ........................................................... 2, c6 Y+ d; [" {5 E. K4 n, D
3. Fabrication of MOS Transistor ..................................... 5
# `2 }% j/ ~- H- c1 C$ ^4. Layout a Single Transistor .......................................... 11+ f% U+ B. k4 k0 r/ d% Y& U) j
First Stroke The basic transistor layout ..................... 12; I/ X3 h5 s3 d6 t7 `( X
Second Stroke Compact the transistor layout ................ 13
/ \& B5 h6 B" @& q7 WThird Stroke Speed up the transistor ........................... 172 ~, a7 q4 w$ f# G& Q$ [% M( T
Fourth Stroke Clean up the substrate Disturbances ...... 207 @ V; N$ ^2 }! |. q" ^% [
Fifth Stroke Balancing area, speed and noise ............ 268 q$ z3 t" ?. F3 m8 X5 n
Sixth Stroke Relief the stress ...................................... 29 W# i) S) e9 c) K g9 S
Seventh Stroke Protect the gate ...................................... 307 z2 x( O# x8 ?6 }; O$ ?
Eighth Stroke Improve yield ..........................................32% V7 P- t& z: Z) K2 g8 ]
5. Layout Several Transistors ......................................... 34
& J8 g: p. M0 |1 H, C' Q6 lEighth Stroke Improve yield...........................................35
. B0 q, i5 F S$ ]! {Re-visit
1 w& P' v4 L% V7 {7 {( r+ [( b5 |Ninth Stroke Close proximity .......................................36( g6 ^! |$ |7 |1 ]+ `
Tenth Stroke Interdigitated layout ............................... 36
& F' E+ } V- H. H6 b; pEleventh Stroke Dummy transistor ................................... 413 e$ R8 j2 }1 Y% ]& p$ m" l
Twelfth Stroke Two-dimension interdigitated layout ..... 43
6 I8 }5 r& P: nThirteenth Stroke Guard ring for the matched transistors ... 45$ O9 r. T& h: I, }" t
Fourteenth Stroke Keep NMOS away from N-well ............ 45
3 j$ W% T1 l! T1 F4 AFifteenth Stroke Orientate the transistor ........................... 46
, {$ j1 M: Z2 z1 _2 i( D$ gSixteenth Stroke Match the interconnects ......................... 47( A& H3 n3 p! l& z* n
Seventeenth Stroke The unmatchable .................................... 50/ p4 i: @6 x# \
6. Verifying the Transistor Layout ................................. 520 f0 ^: @5 Q3 |' K1 x$ S }
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[ 本帖最後由 semico_ljj 於 2008-11-1 04:01 PM 編輯 ] |
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