關於cell-based 流程的DRC問題

ywchywch

請問各位大大
) c% O1 K7 S3 @& y我用TSMC18的design kit作cell-based layout的練習，軟體是用encounter，大部分的步驟是依照CIC所提供的Lab去做，完成之後用我的GDS檔去做DRC，會出現下列的DRC ERROR，而且是M1~M5、via1~via5都會有這方面的error，因為error的數目頗大，不太可能用人工去debug，所以我想請問有經驗的大大們，能不能告訴我最大的問題點在哪裡？以及這些錯誤代表什麼？要如何debug比較適合？
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先謝謝各位大大了!!感激不盡!!

1. M2.W.1 { @ M2 width < 0.28
) k. E. P, n7 @& B  INT M2 < 0.28 SINGULAR REGION ABUT < 90
/ E. L! w3 t) k0 V' {}

2 V* T+ P$ a& ^) d3 Q3 C# L/ U2. M2.S.1 { @ M2 spacing < 0.28
1 a( p+ I2 b9 s9 A/ w: W  EXT M2 < 0.28 ABUT < 90 SINGULAR REGION
2 R" B  f" ]% p# l& J$ W}

; s1 x1 v7 G6 L! R8 e3. M2.S.2 { @ Wide M2 (>10um) min. to M2 < 0.6 um
/ m, e3 ?' {: y2 [6 x0 E  h  M2_S5 = SHRINK (SHRINK (SHRINK (SHRINK M2 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5
8 _- f5 N8 e. Z4 N  M2_G5 = GROW (GROW (GROW (GROW M2_S5 RIGHT BY 5) LEFT BY 5) TOP BY 5) BOTTOM BY 5
  M2_Wide = M2_G5 AND M2

+ }4 u1 w' J2 j1 J( }  M2_Exp = SIZE M2_Wide BY 1 INSIDE OF M2 STEP 0.196
  M2_Branch = M2_Exp NOT M2_Wide
! C! U6 j2 t% [4 q  M2_Branch_edge = M2_Branch COIN INSIDE EDGE M2
: L/ K- I; g5 l" b( E& R  M2_Check = M2 AND (SIZE M2_Exp BY 0.6)
: b* ^3 r, Y4 `0 y! u2 J! U. U  M2_Else = M2_Check NOT INTERACT M2_Exp
  M2_Extend = M2_Check NOT M2_Exp
7 x5 \2 \. _: a) o% l
/ A. z+ i5 z8 e% B' S2 g  EXT M2_Wide M2_Else < 0.6 ABUT >0 <89.5 REGION
  ~  }! }; t6 i* X0 M8 v  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 OPPOSITE REGION
, }: Q6 F1 Q4 R* k; ?4 z  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 CORNER REGION
  EXT M2_Branch_edge M2_Else < 0.6 ABUT >0 <89.5 PROJ==0 REGION
! n6 T0 c. r4 b7 |3 s0 T5 A  A = EXT M2_Exp < 0.6 ABUT > 0 < 89.5 SPACE REGION
6 \. V+ ]5 k6 _8 |  A NOT INTERACT M2_Extend
: W4 S1 ?9 {& M" p& x}
4. M2.E.1 { @ Min extension of a M2 region beyond a VIA1 region is 0.01 um
   ENC VIA1 M2 < 0.01 ABUT<90 SINGULAR
; m5 |$ ]7 ~$ ]4 l( t+ A   VIA1 NOT M2   
* _' \" p' s0 |' z. N, B% @}

5. M2.E.2 { @ Min extension of M2 end-of-line region beyond VIA1 region is 0.06um
" i$ }& ?  N+ [4 v, W0 u# n   X = ENC [VIA1] M2 < 0.06 ABUT < 90 OPPOSITE                // a narrow side
   INT X < 0.26 ABUT == 90 INTERSECTING ONLY       // adjacent narrow sides
}
/ @5 N+ |6 d; S/ _
2 C% M1 u6 M! I$ s+ M" r0 Z6. M2.A.1{ @ Min M2 area region < 0.202
  AREA M2 < 0.202
& S! I- l- D( y! t: c- D. ?$ t  I}
% m$ m8 _! l- U. ~// Density check M2.R.1 included at the end of this file
// VIA2 checks
//=============
+ t6 `# E0 n! ^
- ?+ ^. B: e, w1 p7. VIA2.W.1 { @ VIA2 must be 0.26 x 0.26 um
6 S' D. |- Y0 {) `& x+ o  A = NOT RECTANGLE VIA2 == 0.26 BY == 0.26 ORTHOGONAL ONLY
  A OUTSIDE RNGX   // exclude from metal fuse protection ring area
}

8. VIA2.S.1 { @ VIA2 SPACING < 0.26
0 F2 |# l; P: W+ \4 K  EXT VIA2 < 0.26 ABUT < 90 SINGULAR REGION
0 c8 U1 _2 U8 K' b}
% e, @+ {4 O, p) h8 m
% z1 _5 [8 a  |/ F( Y' e  _9. VIA2.E.1 { @ Min extension of a M2 region beyond a VIA2 region is 0.01 um
  ENC VIA2 M2 < 0.01 ABUT<90 SINGULAR
  VIA2 NOT M2   
2 w3 B  O1 \. x7 N}
" V. L( t! u5 ?! H2 {
* D) k0 F# e; t  P10. VIA2.E.2 { @ Min extension of M2 end-of-line region beyond VIA2 region is 0.06 um
. ~+ ~; M6 ~; s- }   X = ENC [VIA2] M2 < 0.06 ABUT < 90 OPPOSITE         // a narrow side
   INT X < 0.26  ABUT == 90 INTERSECTING ONLY     // adjacent narrow sides
}

motofatfat

我猜你試用APR軟體RUN出來ㄉ
應該是相同NET ㄉMetal space 和 via extension
不夠的問題,通常會用 skill file 來修正

michael6172

我覺得你打電話去CIC問工程師會比較快吧 ...