Altera Cyclone II (EP2C35F672C6)燒錄

difgor0426 · 發表於 2008-3-6 11:03:56

剛拿到這塊kit，寫了一個測試sw跟led
//==================================================//
`timescale 1 ns/1 ns

  module  test_001(
               D,
               Q,
               clk,
               reset,
               QB
               );
input reset, clk;
input [3:0] D;
output  [7:0] Q;
output  [7:0] QB;
wire [7:0] Q;
wire [7:0] QB;
reg    [7:0] X;
reg    [7:0] a;

always@(D)
  begin
      case(D)
         4'b0000 :  X = 8'b0000_0000;
         4'b0001 :  X = 8'b0000_0011;
         4'b0010 :  X = 8'b0000_1100;
         4'b0100 :  X = 8'b0011_0000;
         4'b1000 :  X = 8'b1100_0000;
         default :  X = 8'b1100_0011;
      endcase
  end

assign  Q = a;
assign  QB = ~a;

always@(posedge clk or negedge reset)
  begin
   if(!reset)
      a = #1 1'b0;
   else
      a = #1 X;
  end

  endmodule
//===========================================================//
然後以下是Quartus產生的qsf檔。
//===========================================================//
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors.  Please refer to the
# applicable agreement for further details.

# The default values for assignments are stored in the file
#             test_001_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#             assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.

set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name TOP_LEVEL_ENTITY test_001
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:57:03  MARCH 06, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name USER_LIBRARIES "D:\\Altera II\\970305\\test\\1/"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672
set_global_assignment -name VERILOG_FILE old_test_001.v
set_location_assignment PIN_Y11 -to D[0]
set_location_assignment PIN_AA10 -to D[1]
set_location_assignment PIN_AB10 -to D[2]
set_location_assignment PIN_AE6 -to D[3]
set_location_assignment PIN_AC10 -to Q[0]
set_location_assignment PIN_W11 -to Q[1]
set_location_assignment PIN_W12 -to Q[2]
set_location_assignment PIN_AE8 -to Q[3]
set_location_assignment PIN_AF8 -to Q[4]
set_location_assignment PIN_AE7 -to Q[5]
set_location_assignment PIN_AF7 -to Q[6]
set_location_assignment PIN_AA11 -to Q[7]
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_location_assignment PIN_M21 -to reset
set_location_assignment PIN_P25 -to clk
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_design_synthesis
//=================================================================================================//
我的問題是，不知道為何怎麼樣都燒不進kit裡，
% A2 j$ y7 I# M6 ?7 M1 F已經排除並非JTAG跟KIT的問題！, S8 M* V, ~, W3 d! P) E1 Z) Y$ T
請各位先進一起來分析一下！

ikki · 發表於 2008-3-6 11:10:08

把programmer的錯誤訊息post出來看看, 光看qsf, 無法知道program的問題....

difgor0426 · 發表於 2008-3-6 11:13:59

只有WARNING/ ]+ f. }$ [) R! J* m
沒有ERROR
% h( n2 j) A" N6 l! Z這就是我感到奇怪的地方

ikki · 發表於 2008-3-6 12:02:28

所以是有成功??
不然把program的畫面抓下來看看..

difgor0426 · 發表於 2008-3-6 13:31:45

這是program的畫面

這是assignment pin的畫面

這是燒錄下載到kit的畫面

####################################################
到這都很順利，, z d3 S- C* R6 C+ [
但是~kit就是不動作！！

ikki · 發表於 2008-3-6 14:05:19

檢查看看clock pin 是不是assign錯?
導致電路不動...

difgor0426 · 發表於 2008-3-6 14:11:37

確定沒有！我對著這塊kit的手冊在assign的

michael6172 · 發表於 2008-3-6 16:12:16

你那是要做 signaltap 的lab 吧

看看文件中的設定有沒有遺漏的部份

difgor0426 · 發表於 2008-3-6 16:54:09

在我關閉project的時候，會出現以下3個畫面，是否我的signal沒設定好才會使KIT無法動作！

sieg70 · 發表於 2008-3-7 09:41:44

雖然我夠菜了, 但似乎幫的上一點, 所以我就講一點, 還不懂的feature不要亂開啟
上面signaltap2跟in-system memory content editor不要亂開,
特別是signaltap2開了又沒作正確設定, 就會出現最後面關project時的三個畫面
發展板的manual要K完, 有沒特別的jumper要設mode?
另外, 下載後, 發展板上config_DONE的燈有沒有亮? 有亮的話就是有正確下載,
那就是你的設計的問題,
這電路你期待會在板子上看到什麼動作? 是否你忘了要用手去扳動對應的D的switch提供輸入? 合成過的電路有沒利用RTL view看看電路是否是你要的?

difgor0426 · 發表於 2008-3-7 11:52:24

感謝各位的意見~
同樣的描述~
我放到altera另外一塊kit→EP2C20F484C8(茂倫)
所得出的結果就是我要的~
差別只在PIN的ASSIGN
這樣子可能會認為KIT有問題~
所以~
我又重新寫了一個
放到altera EP2C35F672C6這塊KIT~

居然可以動作了~
以下就是這段硬體的VERILOG HDL
`timescale 1 ns/1 ns
module chip_top (
               clk,
               rst_b,
               cnt,
               seg,
               a,
               sel,
               seg_u9,
               rst,
               clock,
               );


  input  clk;
  input  rst_b;
  input  a, sel, rst, clock;
  output [7:0] cnt;
  output [7:0] seg;
  output [7:0] seg_u9;
  reg [7:0] cnt;
  reg [7:0] seg;
  reg [7:0] seg_u9;
  reg [40:0] clk_cnt;
  reg [40:0] clk_seg;
  reg [40:0] clk_seg_u9;
wire clk_cnt_end = clk_cnt[20];
wire clk_seg_end = clk_seg[20];
  wire clk_seg_u9_end = clk_seg_u9[20];


//---------------------------------------------------------------
  always @(posedge clk or negedge rst_b)
if (!rst_b)
            clk_cnt <= 0;
else
         clk_cnt <= clk_cnt + 1;

  always @(posedge clk_cnt_end or negedge rst_b)
if (!rst_b)
            cnt <= 0;
else
            cnt <= cnt + 1;

//---------------------------------------------------------------

// always @(posedge clk or negedge rst_b)
// if (!rst_b)
//             clk_seg <= 0;
// else
//             clk_seg <= clk_seg + 1;

// always @(posedge clk_seg_end or negedge rst_b)
// if (!rst_b)
//             seg <= 0;
// else
//             seg <= seg + 1;
//---------------------------------------------------------------
//===============================================================
//  always @(posedge clk or negedge rst_b)
// if (!rst_b)
//             clk_seg_u9 <= 0;
// else
//             clk_seg_u9 <= clk_seg_u9 + 1;

//  always @(posedge clk_seg_u9_end or negedge rst_b)
// if (!rst_b)
//             seg_u9 <= 0;
// else
//             seg_u9 <= seg_u9 + 1;
//===============================================================
always@(sel or a)
begin
      if  (sel == 1'b1)
            seg_u9 = 8'b0111_1001;
end
   always@(sel or a)
begin
      if  (sel == 1'b1)
            seg = 8'b0010_0100;
end
//===============================================================

endmodule

tommywgt · 發表於 2008-3-11 12:01:56

嗯, 一個問題丟出來後會有很多大大都幫忙, 社群真是個好地方

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[問題求助] Altera Cyclone II (EP2C35F672C6)燒錄

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社群真是個好地方