關於undersampling ADC的問題

jeffsky

設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
5 j0 X2 ?% ]) i4 p  [3 [# \; f# R6 w或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

jeffsky

原帖由 jeffsky 於 2007-11-8 02:07 PM 發表
設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？/

DennyT

17MHz 的 tone 會不會是系統OSC or XTAL 的 16.667MHz clock feedthrough noise?

+ U8 M+ F- i# U+ F  {8 }因為即使是under sampling, alias image in first order term: (FS=54MHz, Ft=44MHz, Nyquist band=27MHz)
0 X+ [3 V/ J0 J5 X! K/ {: H! VFS-Ft=54-44=10MHz
( F' N( ]+ r( A: TFS+Ft=54+44=98MHz (folding 回 Nyquist band=10MHz)

2nd order term:
( A7 w8 n$ P9 ~9 Y2 W2 D5 Y2FS-Ft=108-44=64MHz (folding 回 Nyquist band=10MHz)
2FS+Ft=108+44=152MHz (folding 回 Nyquist band=10MHz)
* l5 N* o1 T8 l! r|FS-2Ft|=54-88=34MHz (folding 回 Nyquist band=20MHz)
FS+2Ft=54+88=142MHz (folding 回 Nyquist band=20MHz)
5 @0 z% Y# ?# ^/ \$ J0 l, B
2nd~7th Harmonic:
2nd = 20MHz
+ g2 X5 U, P- A/ u3 l3rd = 30MHz  (folding 回 Nyquist band=24MHz)
" [5 D) y. {$ p4th = 40MHz  (folding 回 Nyquist band=14MHz)
( g. |# S! U- V5th = 50MHz  (folding 回 Nyquist band=4MHz)
6th = 60MHz  (folding 回 Nyquist band=6MHz)
7th = 70MHz  (folding 回 Nyquist band=16MHz)
* A+ n0 @) [4 o9 s' ~% ~7 _你附的Frequency domain plot 在6th之後已在noise floor之下了, 故之後的harmonic可略去不計,
" O. [* t3 O5 g2 D1 ?% C# i. U# ]但是就是沒有17MHz的theoretical noise source.
來個Maxim AN928 anti-aliasing filter的文件:
& j/ t, W+ F5 ~; M
[ 本帖最後由 DennyT 於 2007-11-10 12:00 AM 編輯 ]

jeffsky

Thank you for your kind reply.
I have ever seen a paper or something else to say that when the signal frequency approaches the sample rate, the beat frequency is easy to appear at Fsig-Fs/2, for example, this frequency is 17MHz. It is as if sampling frequency is 27MHz. It is really a puzzle.

DennyT

有此一說:
當Fin接近於Fs/2時, ADC sample的電壓slew at full scale, 此時奇數點之間的壓差其實很小 (偶數點亦同), 但是相鄰兩點間的壓差卻很大, 測試上又稱為ADC envelope test, 而在此測試中被引進來的 "beat frequency" 會被視為noise, 使SNR下降.

也就是說, 若ADC內front end的PGA or buffer Amp slew rate不足, 此缺陷便很容易在此測試中被突顯出來.
8 Y/ O. D( \1 X' D  m& J$ j7 P
' w- L6 T' b# U4 e( G. @就系統面而言, 拉高ADC的AVDD看看有沒有救, (ADC PAD_VDD反而要調低, 除了降EMI外也可拉低系統noise floor).
, c( W% o, T, @5 h) B5 m* l
  C! y6 R- J) g- W, w[ 本帖最後由 DennyT 於 2007-11-12 10:29 PM 編輯 ]

jeffsky

I am really thankful to DennyT's reply, it is a reasonable and constructive explanation on this issue. I will try to pull higher supply voltage to see if it can be relieved or removed or not. Thank you very much.