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This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter* M4 M9 q6 X* W+ o' x5 p4 |
Attenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
+ G$ ?6 G0 c: {8 Mon par with commercially available PLLs, while being relatively simple to design and use as6 @) G3 U( Q! R* p! ^" \" D
an on-chip solution. The main difference between the JAC and PLLs is that the JAC does3 P0 Y! U# M/ C h6 }) `1 k2 z
not guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In
+ w+ @+ M3 g3 dthe following sections the effects of jitter, present methods to reduce jitter, and application
! k+ j3 a @, ^2 \0 @; d0 ^of the JAC will be discussed.3 a0 `6 _6 o& ]
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