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Senior Physical Design Engineer5 |7 S" v0 r6 ~( W. `* c1 s
公 司:A famous IC company8 ?$ [0 G* ~" w! V
工作地点:南京# A# h5 h; C- c# U7 U3 n
0 i$ q- g8 `3 [1 m0 OKey Responsibilities & J! X$ t; {# y# i
Depending on experience, key responsibilities will involve some of the following: + u( {0 p8 G3 A
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
8 }$ h# A! ?4 ^3 t" V( iAs a key member of physical design team, your will work on one of most advanced and the most complex chip designed. 6 F! H+ e& B. ]) O: G% t
Leading a team of physical design engineers and resolving the technical related issues. L6 X9 y2 w% D% D
Crosstalk analysis, power analysis, and static timing analysis.
- Y1 `" W2 v/ x+ |; MWrite scripts in Tcl to improve productivity. , E2 t1 r* A7 e+ b1 h' G9 b
$ Z$ P+ t8 d/ R9 C. t+ M$ r9 `Experience: 5+ years in physical implementation engineering 7 `/ V2 d8 t4 E7 d) |& U' [
( R! P4 \6 S; ?* ]: HEssential skills
) w' ?( y5 D) B! QMS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills ! Q# Q9 q8 G: E+ `, V0 H
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation. $ f# F# X6 R) {; T' ~- @0 R
Good programming skill. Capable of writing Tcl or Perl. : Q3 C, \+ [4 }/ Y. i; f
Familiar with synthesis, static timing analysis.
3 y5 i. f$ Y. T! W2 @7 ^Self-motivated team worker, good verbal and written communication skills in English. & `9 }7 G/ |7 C( z& q& R3 w
Technical and team leadership proffered. Previous management experience highly desired. 3 k4 S2 ~5 m3 C( @ w! k F
Experience with synthesis, DFT, and verification is preferred. |
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