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Senior Digital Design Engineer: j% ^& |% q0 c! f' d
- n. R; r- e( P" E. {# \公 司:A famous European IC company
- S; M' _8 @! c0 v I6 o j工作地点:上海
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, {' o( }! I* P3 w e2 h/ m* fJob description 0 }+ i; P$ b: W$ o; e0 D: @
- define system partitioning of s/c circuits and system ; W/ {3 h, [* ?* K7 V$ I
- define HW/SW co-partitioning {# M, g2 [6 _7 ]1 A
- provide technical feasibilities based on system simulation and/or FPGA based demonstrator
: G0 C) g4 K" `1 S0 j7 F7 }- propose new technical solutions on s/c and system level
, r, m/ x3 h9 X& u6 ^- design digital part of mixed signal (smart power) ASICs
, \ K+ o* b/ j1 w$ V* g- {- close cooperation and interaction with international teams & h2 n( j* N" k2 G9 ]
- coach junior engineers
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( ~: R9 @$ Q" a8 aRequired knowledge competencies and attributes ( l8 }2 _/ Z5 m' w4 }4 A6 x* E
- master degree in microelectronic circuits or systems, Communications, Computer Engineering (or equivalent) : w- y0 N+ A0 g& t1 i* M u, J
- > 5ys experience in digital design 1 ?& o" U/ ]$ S W
- good understanding of ASIC mixed signal flow (Cadence based) $ @9 m$ _& s" w0 S8 C [
- strong background in HDL coding, verification and toplevel integration ' g. n4 ]5 z+ r/ k1 o* I* G2 B
- good understanding of communication interfaces used in Automotive (SPI, CAN, LIN, Flexray) " Y$ ?' |$ {, G6 l/ D1 t! k7 [6 j
- experience in FPGA development % i0 r W2 ^; C' R$ ]
- very good communication skills (written, oral)
2 c. D6 w# l5 e$ C- self motivated and high level of flexibility
, D- c# j1 T f- foreign languages: English, German (not a must) |
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