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This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter* p" m0 p! X' w, J4 B! B8 e
Attenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
% I5 G6 `% \% f. h, l) ]. won par with commercially available PLLs, while being relatively simple to design and use as
- Y" Q' l" d8 f& o" w3 x1 V. w) ]/ Jan on-chip solution. The main difference between the JAC and PLLs is that the JAC does$ j" ~" t6 [8 ]4 K% v
not guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In
- _" b/ ]* D1 ?7 q+ Ethe following sections the effects of jitter, present methods to reduce jitter, and application" t a2 y- _, o" L# A2 j8 J
of the JAC will be discussed.
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