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AMD Geode LX 800@0.9W處理器
General Features' A2 v0 ]7 |4 {3 C
■ Functional blocks include:" K# Q4 j+ V3 Q+ n" a N3 p
— CPU Core+ C/ V" e$ _: g+ B1 O
— GeodeLink™ Control Processor/ o) |" c" D/ M+ `+ g# u+ B
— GeodeLink Interface Units+ e& f# O6 B/ L, ]% |$ q
— GeodeLink Memory Controller
4 }, V. s) _" O2 o— Graphics Processor2 k' O, d& ?+ V
— Display Controller# r! u, A- K, `& f
— Video Processor% U$ C/ k& D! Y; i0 q3 d
– TFT Controller/Video Output Port
4 E, u' H. W. j$ S) o8 \— Video Input Port
. p: h& T( w+ v# o7 f) F' E— GeodeLink PCI Bridge5 G9 G5 o( _ K9 @" U- }/ B2 o
— Security Block7 E/ l# f( \4 i0 I7 X' y- Y, S
■ 0.13 micron process& U1 c. [3 ?% e
■ Packaging:0 Q: X, _! u; o: K5 h, K
— 481-Terminal BGU (Ball Grid Array Cavity Up) with
4 S6 N! Q) c3 }# n8 @% l8 Kinternal heatspreader
! u8 l' B) b% j+ c+ n■ Single packaging option supports all features; Q B) Q+ n# f8 h" Q+ }8 B2 P
CPU Processor Features
7 J5 J6 o( t$ f■ x86/x87-compatible CPU core6 d& x8 s- y) v5 G4 J
■ Performance:
. E9 Z; H' ]' m0 Z: U- e— Processor frequency: up to 500 MHz
+ ?; I& v# x: j— Dhrystone 2.1 MIPs: 150 to 4500 R; b4 J! |' k2 D- v
— Fully pipelined FPU
! M) h" _" B0 c6 t) y# t; F% ^+ i/ l■ Split I/D cache/TLB (Translation Look-aside Buffer):- _0 z7 H6 f3 _3 l1 `; s6 a7 ?
— 64 KB I-cache/64 KB D-cache" O" J# G" [- F( c; N, M) w
— 128 KB L2 cache configurable as I-cache, D-cache,
) r" w$ E6 |( S( O1 D7 E. S1 wor both
5 I, T, l2 w. y! Z! Q9 _■ Efficient prefetch and branch prediction. K; h0 D: Y5 k) S3 |- g
■ Integrated FPU that supports the MMX® and3 \( E& {, N3 Z, H
AMD 3DNow!™ instruction sets
" ^/ m7 u( b( |# h+ S, r' _■ Fully pipelined single precision FPU hardware with
* H( C! I N0 [2 Wmicrocode support for higher precisions
6 b) x8 s) {. b! _% v4 h/ vGeodeLink™ Control Processor. R H* r0 w4 ^0 L- L
■ JTAG interface:9 g% Q, \) N% o# d- q! e0 z
— ATPG, Full Scan, BIST on all arrays4 ?" b, e7 a. q& w/ H, v( |
— 1149.1 Boundary Scan compliant" |$ x/ x/ o* P6 U Z5 I$ F
■ ICE (in-circuit emulator) interface
. [0 D8 U$ s V8 w" T) C■ Reset and clock control% C) x! d S- x! ]
■ Designed for improved software debug methods and
) k B# w! e2 V, xperformance analysis
% o0 N) z0 R) l5 n, h■ Power Management:; R% ?6 Z: M7 p8 m
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @" x" b4 Z$ z7 H/ ^
500 MHz max power9 f' h" R% D0 V8 h" d
— GeodeLink active hardware power management
7 K% v* Z5 E5 N. d' z- a" b. U— Hardware support for standard ACPI software power
* r, m: s/ \, Y! X9 lmanagement
8 ^4 T' e# d1 F8 g- Q! P' c— I/O companion SUSP/SUSPA power controls9 g; ~7 @1 P/ ^# x7 m
— Lower power I/O4 X; A/ k2 Z u" ?& ~' B0 c
— Wakeup on SMI/INTR5 A' P- E @+ ]. J1 O: I: \* d
■ Designed to work in conjunction with the* m, u7 S r% W
AMD Geode™ CS5536 companion device2 ?( k2 X7 A9 z
GeodeLink™ Architecture) q4 i) e' R8 D% M, E% G
■ High bandwidth packetized uni-directional bus for
6 _% Z' i, K! L! D, `7 S( g2 }internal peripherals+ ]% L' |" o( ]2 w! V
■ Standardized protocol to allow variants of products to be. R; |1 p! E" G6 }
developed by adding or removing modules
0 B' C5 z$ h' x- N3 d* m4 ~, y- t( g■ GeodeLink Control Processor (GLCP) for diagnostics
& o- n3 l; O7 s0 _6 W1 u: [. q0 {0 |' Zand scan control
& g6 c5 j/ l4 t- Y4 V; f9 K■ Dual GeodeLink Interface Units (GLIUs) for device interconnect. w% k4 _, G* ?' U) o
GeodeLink™ Memory Controller
. K0 _8 B5 Y% J; D) Y■ Integrated memory controller for low latency to CPU and
: `1 ^7 k) `9 n! }/ Y" {on-chip peripherals# v9 }/ t' g- g0 M
■ 64-bit wide DDR SDRAM bus operating frequency:
- T3 L8 M8 a# _. H p4 L— 200 MHz, 400 MT/S
; D5 w7 {. Z( Y+ f1 v% S0 V% s■ Supports unbuffered DDR DIMMS using up to 1 GB6 o% s0 U5 ~. z7 w7 n% t4 o4 |
DRAM technology: H3 [" F- U. b/ y
■ Supports up to 2 DIMMS (16 devices max)3 e% a, M3 v! B4 r% }" p! ?; w
2D Graphics Processor
+ j0 n, j6 a/ M4 c7 i) b1 w! |■ High performance 2D graphics controller
$ @7 z1 j C: z1 V/ h7 y■ Alpha BLT3 r; ~2 N, z7 P, B7 P
■ Microsoft® Windows® GDI GUI acceleration:4 V7 t# I: k& W$ W
— Hardware support for all Microsoft RDP codes
( f/ C+ t. B/ \9 w; o■ Command buffer interface for asynchronous BLTs
a, j# a) N& i# b' w4 Z# a7 U■ Second pattern channel support
' P0 p# e' Z' `■ Hardware screen rotation |
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