Circuit and Layout Co-Design for ESD Protection in BCD

semico_ljj

Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
9 n* M& D1 C9 P5 A  I! o2 D% a, u
5 H  d% T, c6 l# q; m7 C7 n4 MWen-Yi Chen, Student Member, IEEE, and Ming-Dou Ker, Fellow, IEEE
0 F" {! w0 |8 e5 J; ^( i# H
Abstract—The n-channel lateral double-diffused metal–oxide–
semiconductor (nLDMOS) devices in high-voltage (HV) technologies
! q1 W" n. f# ?8 xare known to have poor electrostatic discharge (ESD)
% e0 k  L5 l9 Nrobustness. To improve the ESD robustness of nLDMOS, a co-design
method combining a new waffle layout structure and a trigger
circuit is proposed to fulfill the body current injection technique
in this work. The proposed layout and circuit co-design method
; g# e' W9 K1 ]8 }+ t0 N. u8 Y# Son HV nLDMOS has successfully been verified in a 0.5- m 16-V
bipolar-CMOS-DMOS (BCD) process and a 0.35- m 24-V BCD
process without using additional process modification. Experimental
: ?4 `9 x/ y# t" xresults through transmission line pulse measurement
! o$ w% b6 `3 J7 j. {3 V8 Dand failure analyses have shown that the proposed body current
3 N) G+ {1 x, rinjection technique can significantly improve the ESD robustness
% H! e) J; [; vof HV nLDMOS.

Index Terms—Bipolar-CMOS-DMOS (BCD) process, body
current injection, electrostatic discharge (ESD), lateral double-diffused
metal–oxide–semiconductor (LDMOS).

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