Berkeley的一篇博士论文_Jitter Reduction on High-Speed Clock Signals

hitxiaojun

This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter
7 T/ \. Y1 x3 L# Y; c$ \0 sAttenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
8 L; u; u* h: [( Aon par with commercially available PLLs, while being relatively simple to design and use as
0 E# N6 t1 [" ?/ u. y! q# z& |an on-chip solution. The main difference between the JAC and PLLs is that the JAC does
. V& }$ k: {( U7 U/ a( Mnot guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In
the following sections the effects of jitter, present methods to reduce jitter, and application
+ f8 t& _; u1 {of the JAC will be discussed.
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遊客，如果您要查看本帖隱藏內容請回復

satto0216

謝謝大大…dll&pll的任何相關資料我都很需要
希望可以幫到我，

liyao

剛好工作上碰到jitter measurement問題,下載參閱一下,感恩!!

liyao

> < 我很少上來 沒錢下載 怎麼辦呀!!

anita66

Wow, 新的耶?!真是太讚了, 先下來study看看, 有機會在跟大家分享心得, 3Q~

planet1114

最近在工作上一直被noise所困擾,
下來看看能不能從這有新的啟發.
6 H  y$ y9 b: u: c2 ?+ N先謝啦

godman

謝謝你的分享，希望會有所幫助。

b56389

多看看別人所推薦的paper
: x6 `& C& `1 i研究其的看法與理論
相信對增進自己的實力有幫助的

donnie

Thanks for Sharing
5 H! U& M' p8 O- F$ AThanks for Sharing

donnie

Thanks for Sharing!
" Y2 p, I1 v+ XThanks for Sharing!

ychchip

jitter is important issues in analog ic design.  it must be carefully designed including path match and high speed.

eceking

可惜沒足夠的錢幣............................................................!

anita66

感謝大大無私分享, 不知道有沒有跟Thomas Lee的論點是否相同??3Q~

xp212125o

thank you~
  n  C5 q8 F" h+ K  S  p# M感謝分享
. U# Y5 @1 V& t9 g正好有需要

lyx1982

谢谢分享！收藏了！！！

starfish311

回復 1# hitxiaojun

# x" R2 t; e/ C) U9 O
    謝謝你的分享，希望會有所幫助

ja1688888

剛好需要看PLL jitter 學習一下 感謝

alienwarejian

谢谢
谢谢

microuser

感謝大大無私分享，剛好需要看PLL jitter 學習一下 感謝

microuser

感謝大大無私分享，剛好需要看PLL jitter 學習一下 感謝！